PIC18F4539-ESLASHMLSQTP datasheet(22/322 Pages) MICROCHIP

22 / 322 page

PIC18FXX39

DS30485A-page 20

Preliminary

 2002 Microchip Technology Inc.

TABLE 2-1:

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

2.3

External Clock Input

The EC and ECIO Oscillator modes require an external

clock source to be connected to the OSC1 pin. The

feedback device between OSC1 and OSC2 is turned

off in these modes to save current. There is no oscilla-

tor start-up time required after a Power-on Reset or

after a recovery from SLEEP mode.

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-3 shows the pin connections for the EC

Oscillator mode.

FIGURE 2-3:

EXTERNAL CLOCK INPUT

OPERATION

(EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,

except that the OSC2 pin becomes an additional gen-

eral purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6). Figure 2-4 shows the pin connections

for the ECIO Oscillator mode.

FIGURE 2-4:

EXTERNAL CLOCK INPUT

OPERATION

(ECIO CONFIGURATION)

2.4

HS/PLL

A Phase Locked Loop circuit is provided as a program-

mable option for users that want to multiply the fre-

quency of the incoming crystal oscillator signal by 4.

For an input clock frequency of 5 MHz, the internal

clock frequency will be multiplied to 20 MHz. This is

useful for customers who are concerned with EMI due

to high frequency crystals.

The PLL can only be enabled when the oscillator con-

figuration bits are programmed for HS mode. If they are

programmed for any other mode, the PLL is not

enabled and the system clock will come directly from

OSC1.

The PLL is one of the modes specified by the

FOSC<2:0> configuration bits. The Oscillator mode is

specified during device programming.

A PLL lock timer is used to ensure that the PLL has

locked before device execution starts. The PLL lock

timer has a time-out that is called TPLL.

Ranges Tested:

Mode

Freq

20.0 MHz

15-33 pF

These values are for design guidance only.

See notes following this table.

Crystals Used

20.0 MHz

Epson CA-301 20.000M-C ± 30 PPM

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

2: Rs may be required in HS mode to avoid

overdriving crystals with low drive level

specification.

3: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appro-

priate values of external components, or

verify oscillator performance.

OSC1

OSC2

FOSC/4

Clock from

Ext. System

PIC18FXX39

OSC1

I/O (OSC2)

RA6

Clock from

Ext. System

PIC18FXX39

PIC18F4539-E/MLSQTP датащи(PDF) 22 Page - Microchip Technology

PIC18F4539-E/MLSQTP датащи(HTML) 22 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL