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PIC18F4539-E/MLSQTP датащи(PDF) 82 Page - Microchip Technology

номер детали PIC18F4539-E/MLSQTP
подробное описание детали  Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel
PDF  322 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4539-E/MLSQTP датащи(HTML) 82 Page - Microchip Technology

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PIC18FXX39
DS30485A-page 80
Preliminary
 2002 Microchip Technology Inc.
8.5
RCON Register
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN). For PIC18FXX39
devices, the IPEN bit must always be set (= 1) for the
ProMPT kernel to function correctly. Refer to page 69
for a more detailed discussion on interrupt priorities.
REGISTER 8-10:
RCON REGISTER
R/W-0
U-0
U-0
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN(1)
—
—RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
IPEN(1): Interrupt Priority Enable bit
1
= Enable priority levels on interrupts
0
= Disable priority levels on interrupts (not used)
bit 6-5
Unimplemented: Read as '0'
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-3
bit 3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-3
bit 2
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-3
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-3
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-3
Note 1: Maintain this bit set (= 1).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown



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