PIC18F4539-ESLASHMLSQTP datasheet(91/322 Pages) MICROCHIP

91 / 322 page

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 89

PIC18FXX39

9.3

PORTC, TRISC and LATC

Registers

PORTC is a 6-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a High Impedance mode). Clearing a TRISC bit (= 0)

will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

PORTC.

PORTC is multiplexed with the serial communication

functions (Table 9-5). PORTC pins have Schmitt

Trigger input buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an out-

put, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the corre-

sponding peripheral section for the correct TRIS bit

settings.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register,

without concern due to peripheral overrides.

EXAMPLE 9-3:

INITIALIZING PORTC

PIC18FXX39 devices differ from other PIC18 micro-

controllers in allocation of PORTC pins. For most

PIC18 devices, PORTC is an 8-bit-wide port. For the

PIC18FXX39 family, two of the PORTC pins (RC1 and

RC2) are re-allocated as PWM output only pins for use

with the Motor Control kernel. To maintain pinout com-

patibility with other PICmicro® devices, the remaining

PORTC pins are assigned in a manner consistent with

other PIC18 devices. For this reason, PORTC has pins

RC0 and RC3 through RC7, but not RC1 and RC2.

To maintain compatibility with PIC18FXX2 devices, the

individual port and corresponding latch and direction

bits for RC1 and RC2 are present in the appropriate

registers, but are not available to the user. To avoid

erratic device operation, the values of these bits should

not be modified.

FIGURE 9-7:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

CLRF

PORTC

; Initialize PORTC by

; clearing output

; data latches

CLRF

LATC

; Alternate method

; to clear output

; data latches

MOVLW 0xC

; Value used to

; initialize data

; direction

MOVWF TRISC

; Set RC<3>,RC<0> as inputs,

; RC<5:4> as outputs, and

; RC<7:6> as inputs

Data Bus

WR LATC or

WR TRISC

RD TRISC

Peripheral Data Out

RD PORTC

Peripheral Data In

WR PORTC

RD LATC

Peripheral Output

Schmitt

Port/Peripheral Select(2)

Enable(3)

VSS

VDD

I/O pin(1)

Note 1:

I/O pins have diode protection to VDD and VSS.

Port/Peripheral Select signal selects between port data (input) and peripheral output.

Peripheral Output Enable is only active if Peripheral Select is active.

Data Latch

TRIS Latch

Trigger

PIC18F4539-E/MLSQTP датащи(PDF) 91 Page - Microchip Technology

PIC18F4539-E/MLSQTP датащи(HTML) 91 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL