PIC18F4539-ESLASHMLSQTP datasheet(83/322 Pages) MICROCHIP

83 / 322 page

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 81

PIC18FXX39

8.6

INT0 Interrupt

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 pins are edge triggered: either rising, if the

corresponding INTEDGx bit is set in the INTCON2 reg-

ister, or falling, if the INTEDGx bit is clear. When a valid

edge appears on the RBx/INTx pin, the corresponding

flag bit INTxF is set. This interrupt can be disabled by

clearing the corresponding enable bit INTxE. Flag bit

INTxF must be cleared in software in the Interrupt Ser-

vice Routine before re-enabling the interrupt. All exter-

nal interrupts (INT0, INT1 and INT2) can wake-up the

processor from SLEEP, if bit INTxE was set prior to

going into SLEEP. If the global interrupt enable bit GIE

is set, the processor will branch to the interrupt vector

following wake-up.

The INT0 interrupt is always configured as a high prior-

ity interrupt, and cannot be reconfigured. Interrupt pri-

ority for INT1 and INT2 is determined by the value

contained in the interrupt priority bits, INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>).

Because it is always configured as a high priority inter-

rupt, INT0 cannot be used in conjunction with the

ProMPT

kernel;

must

always

disabled

(INTCON<4> = 0). Failure to do this may result in

erratic operation of the motor control.

8.7

TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh

→ 00h) will set flag bit TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-

ter pair (FFFFh

→ 0000h) will set flag bit TMR0IF. The

interrupt can be enabled or disabled by setting or

clearing enable bit TMR0IE (INTCON<5>). Interrupt

priority for Timer0 is determined by the value contained

in the interrupt priority bit TMR0IP (INTCON2<2>). See

Section 10.0 for further details on the Timer0 module.

8.8

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled or dis-

abled by setting or clearing the enable bit RBIE

(INTCON<3>). Interrupt priority for PORTB interrupt-

on-change is determined by the value contained in the

interrupt priority bit RBIP (INTCON2<0>).

8.9

Context Saving During Interrupts

During an interrupt, the return PC value is saved on the

stack. Additionally, the WREG, STATUS and BSR regis-

ters are saved on the fast return stack. If a fast return

from interrupt is not used (see Section 4.3), the user

may need to save the WREG, STATUS and BSR regis-

ters in software. Depending on the user’s application,

other registers may also need to be saved. Example 8-1

saves and restores the WREG, STATUS and BSR

registers during an Interrupt Service Routine.

EXAMPLE 8-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

W_TEMP

; W_TEMP is in virtual bank

MOVFF

STATUS, STATUS_TEMP

; STATUS_TEMP located anywhere

MOVFF

BSR,

BSR_TEMP

; BSR located anywhere

;

; USER ISR CODE

;

MOVFF

BSR_TEMP,

BSR

; Restore BSR

MOVF

W_TEMP,

; Restore WREG

MOVFF

STATUS_TEMP,STATUS

; Restore STATUS

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