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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC18F4539-E/MLSQTP датащи(PDF) 46 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP датащи(HTML) 46 Page - Microchip Technology |
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46 / 322 page  PIC18FXX39 DS30485A-page 44 Preliminary 2002 Microchip Technology Inc. TMR0H Timer0 Register High Byte 0000 0000 27, 101 TMR0L Timer0 Register Low Byte xxxx xxxx 27, 101 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 27, 99 OSCCON* — — — — — — — * ---- ---0 27 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 27, 191 WDTCON — — — — — — —SWDTE ---- ---0 27, 203 RCON IPEN — —RI TO PD POR BOR 0--1 11qq 25, 50, 80 TMR1H Timer1 Register High Byte xxxx xxxx 27, 103 TMR1L Timer1 Register Low Byte xxxx xxxx 27, 103 T1CON RD16 — T1CKPS1 T1CKPS0 — T1SYNC TMR1CS TMR1ON 0-00 0000 27, 103 TMR2* * * * * * * * * 0000 0000 27 PR2* * * * * * * * * 1111 1111 27 T2CON* * * * * * * * * -000 0000 27 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 27, 125 SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 27, 134 SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 27, 126 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 27, 127 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 27, 137 ADRESH A/D Result Register High Byte xxxx xxxx 187,188 ADRESL A/D Result Register Low Byte xxxx xxxx 187,188 ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON 0000 00-0 28, 181 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 28, 182 CCPR1H PWM Register1 High Byte (Read only) xxxx xxxx 28, 124 CCPR1L* * * * * * * * * xxxx xxxx 28, 124 CCP1CON* — — * * * * * * --00 0000 28, 124 CCPR2H PWM Register2 High Byte (Read only) xxxx xxxx 28, 124 CCPR2L* * * * * * * * * xxxx xxxx 28, 124 CCP2CON* — — * * * * * * --00 0000 28, 124 TMR3H Timer3 Register High Byte xxxx xxxx 28, 109 TMR3L Timer3 Register Low Byte xxxx xxxx 28, 109 T3CON RD16 — T3CKPS1 T3CKPS0 — T3SYNC TMR3CS TMR3ON 0000 0000 28, 109 SPBRG USART1 Baud Rate Generator 0000 0000 28, 168 RCREG USART1 Receive Register 0000 0000 28, 175, 178 TXREG USART1 Transmit Register 0000 0000 28, 173, 176 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 28, 166 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 28, 167 EEADR Data EEPROM Address Register 0000 0000 28, 61, 65 EEDATA Data EEPROM Data Register 0000 0000 28, 65 EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 28, 61, 65 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 28, 62 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition * These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details. Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear. |
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