PIC18F4539-ESLASHMLSQTP datasheet(95/322 Pages) MICROCHIP

95 / 322 page

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 93

PIC18FXX39

9.5

PORTE, TRISE and LATE

Registers

This section is only applicable to the PIC18F4X39

devices.

PORTE is a 3-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISE. Setting a

TRISE bit (= 1) will make the corresponding PORTE pin

an input (i.e., put the corresponding output driver in a

High Impedance mode). Clearing a TRISE bit (= 0) will

make the corresponding PORTE pin an output (i.e., put

the contents of the output latch on the selected pin).

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

PORTE.

PORTE has three pins (RE0/AN5/RD, RE1/AN6/WR

and RE2/AN7/CS) which are individually configurable

as inputs or outputs. These pins have Schmitt Trigger

input buffers.

controls the parallel slave port operation.

PORTE pins are multiplexed with analog inputs. When

selected as an analog input, these pins will read as '0's.

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

EXAMPLE 9-5:

INITIALIZING PORTE

FIGURE 9-9:

PORTE BLOCK DIAGRAM

IN I/O PORT MODE

Note:

On a Power-on Reset, these pins are

configured as analog inputs.

CLRF

PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW

0x07

; Configure A/D

MOVWF

ADCON1

; for digital inputs

MOVLW

0x05

; Value used to

; initialize data

; direction

MOVWF

TRISE

; Set RE<0> as inputs

; RE<1> as outputs

; RE<2> as inputs

Data

Bus

WR LATE

WR TRISE

RD PORTE

Data Latch

TRIS Latch

RD TRISE

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATE

or PORTE

To Analog Converter

Note 1:

I/O pins have diode protection to VDD and VSS.

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