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DS2148 датащи(PDF) 51 Page - Dallas Semiconductor |
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DS2148 датащи(HTML) 51 Page - Dallas Semiconductor |
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51 / 75 page ![]() DS2148/Q48 51 of 75 BASIC INTERFACE Figure 9-1 NOTES: 1) All resistor values are ±1%. 2) In E1 applications, the Rt resistors are used to increase the transmitter return loss (Table 9-1). No return loss is required for T1 applications. 3) The Rr resistors should be set to 60 W each if the internal receive-side termination feature is enabled. When this feature is disabled, Rr = 37.5 W for 75W, 60W for 120W E1 systems, or 50W for 100W T1 lines. 4) See Table 9-1 and Table 9-2 for the appropriate transmit transformer turns ratio (N). RTIP RRING TTIP TRING Receive Line N:1 (larger winding toward the network) DS2148 0.47µF (non polarized) VDD (21) VSS (22) 0.1µF VDD (36) VSS (35) 0.1µF +VDD 0.01µF 2.048MHz (this clock can also be 1.544MHz for T1 only applications) MCLK 1:1 0.1µF Rr Rr Rt Rt Transmit Line 10µF 10µF |
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