DS2148 datasheet(17/75 Pages) DALLAS

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DS2148/Q48

17 of 75

PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS2148T Pin

Numbering) Table 4-4b

ACRONYM

I/O

DESCRIPTION

BIS0/

BIS1

32/

Bus Interface Select Bits 0 & 1. Used to select bus interface option.

BIS0 = 1 and BIS1 = 1 selects hardware mode.

BPCLK

Back Plane Clock. 16.384 MHz output.

CES

Receive & Transmit Clock Edge Select. Selects which RCLK

edge to update RPOS and RNEG and which TCLK edge to sample

TPOS and TNEG.

0 = update RNEG/RPOS on rising edge of RCLK; sample

TPOS/TNEG on falling edge of TCLK

1 = update RNEG/RPOS on falling edge of RCLK; sample

TPOS/TNEG on rising edge of TCLK

DJA

Disable Jitter Attenuator.

0 = jitter attenuator enabled

1 = jitter attenuator disabled

EGL

Receive Equalizer Gain Limit. This pin controls the sensitivity of

the receive equalizer.

EGL E1 (ETS = 0)

0 = -12dB (short haul)

1 = -43dB (long haul)

EGL

T1 (ETS = 1)

0 = -36dB (long haul)

1 = -30dB (limited long haul)

ETS

E1/T1 Select.

0 = E1

1 = T1

HBE

Receive & Transmit HDB3/B8ZS Enable.

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

HRST*

Hardware Reset. Bringing HRST* low will reset the DS2148.

JAMUX

Jitter Attenuator MUX. Controls the source for JACLK. See

Figure 3-1 and Table 4-10.

E1 (ETS = 0)

JAMUX

MCLK = 2.048 MHz

T1 (ETS = 1)

MCLK = 2.048 MHz

MCLK = 1.544 MHz

JAS

Jitter Attenuator Select.

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

L0/L1/L2

Transmit LIU Waveshape Select Bits 0 & 1 [H/W Mode]. These

inputs determine the waveshape of the transmitter. See Table 9-1

and Table 9-2.

LOOP0/

LOOP1

16/

Loopback Select Bits 0 & 1 [H/W Mode]. These inputs determine

the active loopback mode (if any). See Table 4-5.

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