DS2148 datasheet(11/75 Pages) DALLAS

11 / 75 page

DS2148/Q48

11 of 75

PIN DESCRIPTIONS IN PARALLEL PORT MODE (Sorted by Pin Name,

DS2148T Pin Numbering) Table 4-2b

ACRONYM

I/O

DESCRIPTION

Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 =

1), serves as the address bus. In multiplexed bus operation (BIS1 =

0, BIS0 = 0), these pins are not used and should be tied low.

ALE

(AS)

Address Latch Enable (Address Strobe). When using the parallel

port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to

demultiplex the bus on a positive-going edge. In nonmultiplexed bus

mode (BIS0 = 1), should be tied low.

BIS0/

BIS1

32/

Bus Interface Select Bits 0 & 1. Used to select bus interface option.

See Table 4-1 for details.

BPCLK

Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output that is referenced to RCLK selectable via

CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz

output.

CS*

Chip Select. Must be low to read or write to the device. CS* is an

active low signal.

D0 / AD0

D7 / AD7

I/O

Data Bus/Address/Data Bus. In non-multiplexed bus operation

(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus

operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed

address/data bus.

HRST*

Hardware Reset. Bringing HRST* low will reset the DS2148

setting all control bits to their default state of all zeros.

INT*

Interrupt [INT*] pin 23. Flags host controller during conditions

and change of conditions defined in the Status Register. Active low,

open drain output.

MCLK

Master Clock. A 2.048MHz (±50ppm) clock source with TTL

levels is applied at this pin. This clock is used internally for both

clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz

clock source is optional.

See Note 1 on clock accuracy at the end of this table.

Not Assigned. Should be tied low.

PBEO

PRBS Bit Error Output. The receiver will constantly search for a

215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).

Remains high if out of synchronization with the PRBS pattern. Goes

low when synchronized to the PRBS pattern. Any errors in the

received pattern after synchronization will cause a positive going

pulse (with same period as E1 or T1 clock) synchronous with

RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2

registers by setting CCR6.2 to a logic 1.

PBTS

Parallel Bus Type Select. When using the parallel port (BIS1 = 0),

set high to select Motorola bus timing, set low to select Intel bus

timing. This pin controls the function of the RD*(DS*), ALE(AS),

and WR*(R/W*) pins. If PBTS = 1 and BIS1 = 0, then these pins

assume the Motorola function listed in parenthesis (). In serial port

mode, this pin should be tied low.

DS2148 датащи(PDF) 11 Page - Dallas Semiconductor

DS2148 датащи(HTML) 11 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

датащи скачать

ссылки URL