DS2148 datasheet(18/75 Pages) DALLAS

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DS2148/Q48

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ACRONYM

I/O

DESCRIPTION

MCLK

Master Clock. A 2.048MHz (±50ppm) clock source with TTL

levels is applied at this pin. This clock is used internally for both

clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz

clock source is optional. G.703 requires an accuracy of

±50ppm for

both T1 and E1. TR62411 and ANSI specs require an accuracy of

±32ppm for T1 interfaces.

MM0/

MM1

18/

Monitor Mode Select Bits 0 & 1 [H/W Mode]. These inputs

determine if the receive equalizer is in a monitor mode.

See Table 4-8.

Not Assigned. Should be tied low.

NRZE

NRZ Enable [H/W Mode].

0 = Bipolar data at RPOS/RNEG and TPOS/TNEG

1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a

positive going pulse when device receives a BPV, CV, or EXZ.

PBEO

PRBS Bit Error Output. The receiver will constantly search for a

QRSS (T1) or a 215-1 (E1) PRBS depending on whether T1 or E1

mode is selected. Remains high if out of synchronization with the

PRBS pattern. Goes low when synchronized to the PRBS pattern.

Any errors in the received pattern after synchronization will cause a

positive going pulse (with same period as E1 or T1 clock)

synchronous with RCLK.

RCLK

Receive Clock. Buffered recovered clock from the line.

Synchronous to MCLK in absence of signal at RTIP and RRING.

RCL

Receive Carrier Loss. An output which will toggle high during a

receive carrier loss.

RNEG

Receive Negative Data. Updated on the rising edge (CES = 0) or

the falling edge (CES = 1) of RCLK with the bipolar data out of the

line interface. Set NRZE to a one for NRZ applications. In NRZ

mode, data will be output on RPOS while a received error will cause

a positive-going pulse synchronous with RCLK at RNEG. See

Section 8.4 for details.

RPOS

Receive Positive Data. Updated on the rising edge (CES = 0) or the

falling edge (CES = 1) of RCLK with bipolar data out of the line

interface. Set NRZE pin to a one for NRZ applications. In NRZ

mode, data will be output on RPOS while a received error will cause

a positive-going pulse synchronous with RCLK at RNEG. See

Section 8.4 for details.

RT0/

RT1

44/

Receive LIU Termination Select Bits 0 & 1 [H/W Mode]. These

inputs determine the receive termination. See Table 4-9.

RTIP/

RRING

27/

Receive Tip and Ring. Analog inputs for clock recovery circuitry.

These pins connect via a 1:1 transformer to the line. See Section 7

for details.

SCLKE

Receive & Transmit Synchronization Clock Enable.

0 = disable 2.048 MHz synchronization transmit and receive mode

1 = enable 2.048 MHz synchronization transmit and receive mode

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