DS2148 datasheet(12/75 Pages) DALLAS

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DS2148/Q48

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ACRONYM

I/O

DESCRIPTION

RCLK

Receive Clock. Buffered recovered clock from the line.

Synchronous to MCLK in absence of signal at RTIP and RRING.

RD*

(DS*)

Read Input (Data Strobe). RD* and DS* are active low signals.

DS active low when in nonmultiplexed, Motorola mode. See the Bus

Timing Diagrams in Section 12.

RCL/

LOTC

Receive Carrier Loss/Loss of Transmit Clock. An output which

will toggle high during a receive carrier loss (CCR2.7 = 0) or will

toggle high if the TCLK pin has not been toggled for 5

msec ± 2msec

(CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware mode.

RNEG

Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)

or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out

of the line interface. Set NRZE (CCR1.6) to a one for NRZ

applications. In NRZ mode, data will be output on RPOS while a

received error will cause a positive-going pulse synchronous with

RCLK at RNEG. See Section 8.4 for details.

RPOS

Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or

the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the

line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In

NRZ mode, data will be output on RPOS while a received error will

cause a positive-going pulse synchronous with RCLK at RNEG. See

Section 8.4 for details.

RTIP/

RRING

27/

Receive Tip and Ring. Analog inputs for clock recovery circuitry.

These pins connect via a 1:1 transformer to the line. See Section 7

for details.

TCLK

Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to

clock data through the transmit side formatter. Can be sourced

internally by MCLK or RCLK. See Common Control Register 1 and

Figure 3-3.

TEST

3-state Control. Set high to 3-state all outputs and I/O pins

(including the parallel control port). Set low for normal operation.

Useful in board level testing.

TNEG

Transmit Negative Data. Sampled on the falling edge (CCR2.1 =

0) or the rising edge (CCR2.1 = 1) of TCLK for data to be

transmitted out onto the line.

TPOS

Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)

or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted

out onto the line.

TTIP/

TRING

34/

Transmit Tip and Ring [TTIP & TRING]. Analog line driver

outputs. These pins connect via a step-up transformer to the line. See

Section 7 for details.

VDD

21/

Positive Supply. 5.0V ±5%

VSM

Voltage Supply Mode. Should be tied high for 5V operation

VSS

22/

Signal Ground.

WR*

(R/W*)

Write Input (Read/Write). WR* is an active low signal. See the

Bus Timing Diagrams in Section 12.

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