DS2148 datasheet(46/75 Pages) DALLAS

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DS2148/Q48

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FUNCTION OF ECRS BITS AND RNEG PIN Table 8-4

E1 or T1

(CCR1.7)

ECRS2

(CCR6.2)

ECRS1

(CCR6.1)

ECRS0

(CCR6.0)

RHBE

(CCR2.3)

FUNCTION OF ECR

COUNTERS/RNEG1

CVs

BPVs (HDB3 code words not counted)

CVs + EXZs

BPVs + EXZs

BPVs (B8ZS code words not counted)

BPVs + 8 EXZs

BPVs

BPVs + 16 EXZs

PRBS Errors2

NOTES:

1) RNEG outputs error data only when in NRZ mode (CCR1.6 = 1).

2) PRBS errors will always be output at PBEO independent of ECR control bits and NRZ mode and will

not be present at RNEG.

8.4.1 Error Counter Update

A transition of the ECUE (CCR1.4) control bit from 0 to 1 will update the ECR registers with the current

values and reset the counters. ECUE must be set back to zero and another 0 to 1 transition must occur for

subsequent reads/resets of the ECR registers. Note that the DS2148 can report errors at RNEG when in

NRZ mode (CCR1.6 = 1) by outputting a pulse for each error occurrence. The counter saturates at 65,535

and will not rollover.

ECR1 (11H): UPPER ERROR COUNT REGISTER 1

ECR2 (12H): LOWER ERROR COUNT REGISTER 2

(MSB)

(LSB)

E15

E14

E13

E12

E11

E10

ECR1

ECR2

SYMBOL

POSITION

DESCRIPTION

E15

ECR1.7

MSB of the 16-bit error count

ECR2.0

LSB of the 16-bit error count

8.5

Error Insertion

When IBPV (CCR3.1) is transitioned from a zero to a one, the device waits for the next occurrence of

three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error

insertion. See figure 3-3 for details on the insertion of the BPV into the datastream.

When IBE (CCR3.0) is transitioned from a zero to a one, the device will insert a logic error. IBE must be

cleared and set again for another logic error insertion. See figure 3-3 for details on the insertion of the

logic error into the datastream.

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