DS2148 datasheet(19/75 Pages) DALLAS

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DS2148/Q48

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ACRONYM

I/O

DESCRIPTION

TCLK

Transmit Clock. A 2.048 MHz or 1.544 MHz primary clock. Used

to clock data through the transmit side formatter.

TEST

3-State Control. Set high to 3-state all outputs and I/O pins

(including the parallel control port). Set low for normal operation.

Useful in board level testing.

TNEG

Transmit Negative Data. Sampled on the falling edge (CES = 0) or

the rising edge (CES = 1) of TCLK for data to be transmitted out

onto the line.

TPD

Transmit Power-Down.

0 = normal transmitter operation

1 = powers down the transmitter and 3-states the TTIP and TRING

pins

TPOS

Transmit Positive Data. Sampled on the falling edge (CES = 0) or

the rising edge (CES = 1) of TCLK for data to be transmitted out

onto the line.

TTIP/

TRING

34/

Transmit Tip and Ring [TTIP & TRING]. Analog line driver

outputs. These pins connect via a step-up transformer to the line. See

Section 7 for details.

TX0/

TX1

14/

Transmit Data Source Select Bits 0 & 1 [H/W Mode]. These

inputs determine the source of the transmit data. See Table 4-6.

VDD

21/

Positive Supply. 5.0V ±5%

VSM

Voltage Supply Mode. Should be tied high for 5V operation

VSS

22/

Signal Ground.

NOTES:

1) G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an

accuracy of ±32ppm for T1 interfaces.

2) * Denotes active low.

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