PC97338VLJ datasheet(163/221 Pages) NSC

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5.15 BANK 1

TABLE 82. Bank 1 Register Set

In MIR or FIR modes this bit can be used in con-

junction with bit 1 to determine whether a number

of bytes, as determined by the RX_FIFO thresh-

old, can be read without checking the RXDA bit in

the LSR register for each byte. Cleared when a

character is read from the RX_FIFO.

B1 MIR, FIR Modes

FEND_INF – Frame End Bytes in RX_FIFO.

This bit is read-only, and is set to 1 when one or

more Frame End bytes are in the RX_FIFO.

Cleared when no Frame End byte is in the

RX_FIFO.

B2 MIR, FIR Modes

S_EOT – Set End of Transmission.

When a 1 is written into this bit position before

writing the last character into the TX_FIFO, frame

transmission is completed and a CRC + EOF is

sent. This bit can be used as an alternative to the

Transmitter Frame Length register. If this method

is to be used, the FEND_MD bit in the IRCR2 reg-

ister should be set to 1, or the Transmitter Frame

Length register should be set to maximum count.

This bit is automatically cleared by the hardware

when a character is written into the TX_FIFO.

CEIR Mode

S_EOT – Set End of Transmission.

When a 1 is written into this bit position before

writing the last character into the TX_FIFO, data

transmission is gracefully completed. If the CPU

simply stops writing data into the TX_FIFO at the

end of the data stream, a transmitter underrun is

generated and the transmitter stops. In this case,

this is not an error, however the software needs to

clear the underrun before the next transmission

can occur.

This bit is automatically cleared by the hardware

when a character is written into the TX_FIFO.

B3 MIR, FIR Modes

TXHFE – Transmitter Halted on Frame End.

This bit is used only when the transmitter frame-

end stop mode is selected (TX_MS bit in IRCR2

set to 1). It is set to 1 by the hardware when trans-

mission of a frame is complete and the end-of-

frame condition was generated by the TFRCC

counter reaching 0.

This bit must be cleared, by writing 1 into it, to re-

enable transmission.

B4 MIR, FIR Modes

LOST_FR – Lost Frame Flag.

This bit is read-only, and reflects the setting of the

lost-frame indicator flag at the bottom of the

ST_FIFO.

CEIR Mode

RXWDG – Receiver Watch Dog.

Set to 1 each time an infrared pulse or pulse-train

is detected by the receiver.

Can be used by the software to detect a receiver

idle condition.

Cleared upon read.

B5 MIR, FIR Modes

RXBSY – Receiver Busy.

This bit is read-only, and returns a 1 when recep-

tion of a frame is in progress.

CEIR Mode

RXACT – Receiver Active.

Set to 1 when an infrared pulse or pulse-train is

received. If a 1 is written into this bit position, the

bit is cleared and the receiver is deactivated.

When this bit is set, the receiver samples the in-

frared input continuously at the programmed baud

rate and transfers the data to the RX_FIFO.

B6 MIR, FIR, CEIR Modes

TXUR – Transmitter Underrun.

This bit is set to 1 when a transmitter underrun oc-

curs.

It is always cleared when a mode other than MIR,

FIR or CEIR is selected.

This bit must be cleared, by writing 1 into it, to re-

enable transmission.

B7 UART, Sharp-IR, CEIR Modes

CTE - Clear Timer Event

Writing 1 into this bit position clears the TMR_EV

bit in the EIR register. Writing 0 into it has no ef-

fect.

MIR, FIR, SIR Modes

PLD/CTE – Pipeline Load Status/Clear Timer

Event.

Reading this bit returns the pipeline load status. It

is set to 1 by the hardware when a pipeline load

operation occurs. It is cleared upon read.

Writing 1 into this bit position clears the TMREV

bit in the EIR register. Writing 0 into it has no ef-

fect. The write operation has no effect on the

Pipeline Load Status.

Address

Offset

Name

Description

00h

LBGD(L)

Legacy Baud Generator

Divisor Port (Low Byte)

01h

LBGD(H)

Legacy Baud Generator

Divisor Port (High Byte)

02h

Reserved

03h

LCR/

BSR

Link Control /

Bank Select Register

04h - 07h

Reserved

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