PC97338VLJ datasheet(138/221 Pages) NSC

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Bit 0 - Data Strobe Control

Bit 0 directly controls the data strobe signal to the

printer via the STB signal. This bit is the inverse of

the STB signal.

0 - The STB signal is inactive in all modes except

010 and 011. In these modes, it may be active

or inactive as set by the software.

1 - In all modes, STB is active.

Bit 1 - Automatic Line Feed Control

This bit directly controls the automatic feed XT sig-

nal to the printer via the AFD signal. Setting this bit

high causes the printer to automatically feed after

each line is printed. This bit is the inverse of the

AFD signal.

In mode 011, AFD is activated by both ECP hard-

ware and by software using this bit.

0 - No automatic line feed. (Default)

1 - Automatic line feed.

Bit 2 - Printer Initialization Control

Bit 2 directly controls the signal to initialize the

printer via the INIT signal. Setting this bit to low ini-

tializes the printer. The INIT signal follows this bit.

0 - Initialize printer (Default)

1 - No action.

Bit 3 - Parallel Port Input Control

This bit directly controls the select input device sig-

nal to the printer via the SLIN signal. It is the in-

verse of the SLIN signal.

This bit must be set to 1 before enabling the EPP

or ECP modes via bits 0 or 2 of the PCR register.

0 - The printer is not selected.

1 - The printer is selected.

Bit 4 - Interrupt Enable

Bit 4 enables the interrupt generated by the ACK

signal. In ECP mode, this bit should be set to 0.

This bit does not float the IRQ pin.

0 - Masked. (Default)

1 - Enabled.

Bit 5 - Direction Control

This bit determines the direction of the parallel port

when bit 7 of PTR is 1. The default condition is par-

allel port in output mode.

In the PC87338, this bit is a read only bit (return 0)

in ECP modes 000 and 010. In all other ECP

modes, it is a read/write bit.

In the PC97338, this bit is a read/write bit in all ECP

modes.

This bit is a read/write bit in EPP mode. In SPP

mode it is a write only bit. A read from it returns 1.

In SPP Compatible mode and in EPP mode it does

not control the direction. See Table 64.

0 - The ECP is in forward direction.

1 - The ECP is in backward direction.

The ECP drives the PD7-0 pins in the forward di-

rection, but does not drive them in the backward

direction.

The direction bit, bit 5, is readable and writable. In

modes 000 and 010 the direction bit is forced to 0,

internally, regardless of the data written into this

bit.

0 - ECP drives forward in output mode. (Default)

1 - ECP direction is backward.

Bits 7,6 - Reserved

These bits are reserved and are always 1.

4.4.9

Parallel Port Data FIFO (CFIFO)

Offset 400h

The Parallel Port FIFO (CFIFO) register is write only.

A byte written to this register by PIO or DMA is pushed

into the FIFO and tagged as data.

Reading this register has no effect and the data read

is undefined.

FIGURE 81. CFIFO Register Bitmap

4.4.10 ECP Data FIFO (DFIFO) Register,

Bits 7-5 of ECR = 011, Offset 400h

This bi-directional FIFO functions as either a write-

only device (when DCR bit 5 is 0) or a read-only de-

vice (DCR bit 5 is 1).

In the forward direction (bit 5 of DCR is 0), a byte writ-

ten to the ECP Data FIFO (DFIFO) register by PIO or

DMA is pushed into the FIFO and tagged as data.

Reading this register when set for write-only has no

effect and the data read is undefined.

Reset

Required

Parallel Port FIFO

Offset 400h

Bits 7-5 of ECR = 010

765

210

Data Bits

D0 - D7

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