PC97338VLJ datasheet(139/221 Pages) NSC

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In the backward direction (bit 5 of DCR is 1), the ECP

automatically issues ECP read cycles to fill the FIFO.

Reading from this register pops a byte from the FIFO.

Writing to this register when it is set for read-only has

no effect, and the data written is ignored.

FIGURE 82. DFIFO Register Bitmap

4.4.11 Test FIFO (TFIFO) Register,

Bits 7-5 of ECR = 110, Offset 400h

A byte written into the Test FIFO (TFIFO) register is

pushed into the FIFO. A byte read from this register is

popped from the FIFO. The ECP does not issue an

ECP cycle to transfer the data to or from the peripher-

al device.

The TFIFO is readable and writable in both directions.

In the forward direction (bit 5 of DCR is 0) PD7-0 are

driven, but the data is undefined.

The FIFO does not stall when overwritten or underrun

(access is ignored). Bytes are always read from the

top of the FIFO, regardless of the direction bit setting

(bit 5 of DCR). For example if 44h, 33h, 22h, 11h is

written into the FIFO, reading the FIFO returns 44h,

33h, 22h, 11h (in the same order it was written).

FIGURE 83. TFIFO Register Bitmap

4.4.12 Configuration Register A

(CNFGA), Bits 7-5 of ECR = 111,

Offset 400h

This register is read only. Reading CNFGA always re-

turns 100 on bits 2 to 0 and 0001 on bits 7 to 4; bit 3

is a reflection of bit 5 of ASC. Writing this register has

no effect and the data is ignored.

FIGURE 84. CNFGA Register Bitmap

Bits 2-0 - Reserved

These bits are reserved and are always 100.

Bit 3 - Bit 5 of ASC

This bit reflects the value of bit 5 of the ASC con-

figuration register, which has no specific function.

Bit 5 of ASC may be used at the discretion of sys-

tem programmers, for any purpose. Whatever val-

ue is put in bit 5 of the ASC register will appear in

bit 3 of the CNFGA register.

The CNFGA register bit reflects a specific system

configuration parameter, as opposed to other de-

vices, e.g., 8-bit data word length.

Bit 7-4 - Reserved

These bits are reserved and are always 0001.

4.4.13 Configuration Register B

(CNFGB), Bits 7-5 of ECR = 111,

Offset 401h

Configuration register B (CNFGB) is read only. Read-

ing this register returns the configured parallel port in-

terrupt line and DMA channel, and the state of the

interrupt line.

Writing to this register has no effect and the data is ig-

nored.

321

Reset

Required

ECP Data FIFO

Offset 400h

Bits 7-5 of ECR = 011

Data Bits

D0 - D7

321

Reset

Required

Test FIFO

Offset 400h

Bits 7-5 of ECR = 110

Data Bits

D0 - D7

321

Reset

Required

Configuration Register A

(CNFGA)

Offset 400h

Always 0

Bit 5 of ASC

Bits 7-5 of ECR = 111

Always 0

Always 1

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