PC97338VLJ datasheet(141/221 Pages) NSC

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1 - The FIFO is empty or ECP clock is frozen.

Bit 1 - FIFO Full

This bit continuously reflects the FIFO state, and

therefore can only be read. Data written to this bit

is ignored.

When the ECP clock is frozen this bit is read as 1,

regardless of the actual FIFO state.

0 - The FIFO has at least one free byte.

1 - The FIFO is full or ECP clock frozen.

Bit 2 - ECP Service

This bit enables servicing of interrupt requests. It

is set to 1 upon reset, and by the occurrence of in-

terrupt events.

While set to 1, neither DMA nor the interrupt

events listed below will generate an interrupt. It is

set to 0 by software.

When set to 0, the interrupt setup is “armed” and

an interrupt will be generated on occurrence of an

interrupt event.

While the ECP clock is frozen, it will always return

a 0 value, although it retains its proper value and

may be modified while the clock is frozen.

When one of the following interrupt events occurs

while this bit is 0, an interrupt is generated and this

bit is set to 1 by hardware.

— DMA is enabled (Bit 3 of ECR is 1) and terminal

count is reached.

— FIFO write threshold reached (no DMA -Bit 3 of

ECR is 0; forward direction - bit 5 of DCR is 0,

and there are eight or more bytes free in the

FIFO).

— FIFO read threshold reached (no DMA - bit 3 of

ECR is 0; read direction set - bit 5 of DCR is 1,

and there are eight or more bytes to be read

from the FIFO).

0 - The DMA and the above three interrupts are

not disabled.

1 - The DMA and the above three interrupts are

disabled.

Bit 3 - ECP DMA Enable

0 - Depending on the value of bits 7 and 6 of the

PNP2 register, the selected pin DRQ0, DRQ1

or DRQ2 is in TRI-STATE, and the appropriate

signal DACK0, DACK1 or DACK2 is assumed

inactive.

1 - The DMA is enabled and the DMA starts

when bit 2 of ECR is 0.

Bit 4 - ECP Interrupt Mask

0 - An interrupt is generated on ERR assertion

(the high-to-low edge of ERR). An interrupt is

also generated while ERR is asserted when

this bit is changed from 1 to 0; this prevents

the loss of an interrupt between ECR read

and ECR write.

1 - No interrupt is generated.

Bits 7-5 - ECP Mode Control

These bits set the mode for the ECP device. See

Section 4.5 for a more detailed description of op-

eration in each of these ECP modes. The ECP

modes are listed in Table 71.

TABLE 71. ECP Modes

Mode

Code

Mode Name

Operation Description

Bit

Standard

mode

Write cycles are under

software control.

Bit 5 of DCR is forced to 0

(forward direction) and

PD7-0 are driven.

The FIFO is reset (empty).

Reading DATAR returns the

last value written to DATAR.

PS/2 mode Read and write cycles are

under software control.

The FIFO is reset (empty).

Parallel port

FIFO mode

Write cycles are automatic,

i.e., under hardware control

(STB is controlled by

hardware).

Bit 5 of DCR is forced to 0

internally (forward direction)

and PD7-0 are driven.

ECP FIFO

mode

The FIFO direction is

automatic, i.e., controlled

by bit 5 of DCR.

Read and write cycles to

the device are controlled by

hardware (STB and AFD

are controlled by

hardware).

Reserved

FIFO test

mode

The FIFO is accessible via

the TFIFO register.

The ECP does not issue

ECP cycles to fill or empty

the FIFO.

1 Configuration

mode

CNFGA and CNFGB

registers are accessible.

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