PC97307 datasheet(127/218 Pages) NSC

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127

Parallel Port (Logical Device 4)

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Bits 2-0 - Reserved

These bits are reserved.

Bit 3 - EPP 1.7 ZWS Control

Upon reset this bit is initialized to 0. This bit controls as-

sertion of ZWS on EPP 1.7 access.

There is no ZWS assertion on SPP and on EPP 1.9 ac-

cess. ZWS is always asserted on ECP access.

Control of ZWS assertion on parallel port access, except

in EPP mode, is done via the SuperI/O Configuration 1

0 - ZWS not asserted on EPP 1.7 access.

1 - ZWS asserted on EPP 1.7 access.

Bit 4 - EPP 1.7/1.9 Select

Selects EPP version 1.7 or 1.9.

0 - EPP version 1.7.

1 - EPP version 1.9.

Bit 5 - Reserved

This bit is reserved.

Bit 6 - Channel Address Enable

When this bit is 1, mode is 011, direction is backward,

there is an input command (BUSY is 0), and bit 7 of the

data is 1, the command is written into the FIFO.

Bit 7 - SPP Compatibility

See the Mode Select field (bits 7 through 5 of the ECR

0 - Modes 000, 001 and 100 are identical to ECP.

1 - Modes 000 and 001 of the ECP are identical with

Compatible and Extended modes of the SPP (see

Section 6.1 on page 111), and mode 100 of the

ECP is compatible with EPP mode.

Modes 000, 001 and 100 differ as follows:

000, 001 and 100 – Reading DCR returns pin values of

bits 3-0.

000 and 001 – Reading DCR returns 1 for bit 5.

000, or 001 or 100 when bit 5 of DCR is 0 (forward di-

rection) – Reading DATAR returns register latched

value instead of pin values.

000, 001, and 100, when bit 4 of DCR is 0 – IRQx is

ﬂoated.

001 – IRQx is a level interrupt generated on the trailing

edge of ACK. Bit 2 of the DSR is the IRQ status bit

(same behavior as bit 2 of the STR).

6.5.18

Control4, Second Level Offset 04h

Upon reset this register is initialized to 00000111.

This register enables control of the fairness mechanism of

the DMA by programming the maximum number of bus cy-

cles that the parallel port DMA request signals can remain

active, and the minimum number of clock cycles that they

will remain inactive after they were deactivated.

FIGURE 6-32. Control4 Register Bitmap

Bits 2- 0 - Parallel Port DMA Request Active Time

This field specifies the maximum number of consecutive

bus cycles that the parallel port DMA signals can remain

active.

The default value is 111, which specifies 32 cycles.

When these bits are 0, the number is 1 cycle.

Otherwise, the number is 4(n+1) where n is the value of

these bits.

Bit 3 - Reserved

This bit is reserved.

Bits 6-4 - Parallel Port DMA Request Inactive Time

This field specifies the minimum number of clock cycles

that the parallel port DMA signals remain inactive after

being deactivated by the fairness mechanism.

The default value is 000, which specifies 8 clock cycles.

Otherwise, the number of clock cycles is 8 + 32n, where

n is the value of these bits.

Bit 7 - Reserved

This bit is reserved.

6.5.19

PP Confg0, Second Level Offset 05h

Upon reset this register is initialized to 00h.

FIGURE 6-33. PP Confg0 Register Bitmap

76543210

Reset

Required

Control4 Register

Offset 04h

Reserved

PP DMA Request Inactive Time

PP DMA Request

Second Level

Active Time

76543210

Reset

Required

PP Confg0 Register

Offset 05h

ECP DMA Channel Number

PE Internal Pull-up or Pull-down

ECP IRQ Number

Demand DMA Enable

Bit 3 of CNFGA

Second Level

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