PC97307 datasheet(123/218 Pages) NSC

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Parallel Port (Logical Device 4)

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Reading from this register pops a byte from the FIFO. Writ-

ing to this register when it is set for read-only has no effect,

and the data written is ignored.

FIGURE 6-22. DFIFO Register Bitmap

6.5.9

Test FIFO (TFIFO) Register,

Bits 7-5 of ECR = 110, Offset 400h

A byte written into the Test FIFO (TFIFO) register is pushed

into the FIFO. A byte read from this register is popped from

the FIFO. The ECP does not issue an ECP cycle to transfer

the data to or from the peripheral device.

The TFIFO is readable and writable in both directions. In the

forward direction (bit 5 of DCR is 0) PD7-0 are driven, but

the data is undefined.

The FIFO does not stall when overwritten or underrun (ac-

cess is ignored). Bytes are always read from the top of the

FIFO, regardless of the direction bit setting (bit 5 of DCR).

For example if 44h, 33h, 22h, 11h is written into the FIFO,

reading the FIFO returns 44h, 33h, 22h, 11h (in the same

order it was written).

FIGURE 6-23. TFIFO Register Bitmap

76543210

Reset

Required

ECP Data FIFO

Offset 400h

Bits 7-5 of ECR = 011

Data Bits

76543210

Reset

Required

Test FIFO

Offset 400h

Bits 7-5 of ECR = 110

Data Bits

6.5.10

Configuration Register A (CNFGA),

Bits 7-5 of ECR = 111, Offset 400h

This register is read only. Reading CNFGA always returns

100 on bits 2 through 0 and 0001 on bits 7 through 4.

Writing this register has no effect and the data is ignored.

FIGURE 6-24. CNFGA Register Bitmap

Bits 2-0 - Reserved

These bits are reserved and are always 100.

Bit 3 - Bit 7 of PP Confg0

This bit reflects the value of bit 7 of the ECP PP Confg0

function. Whatever value is put in bit 7 of PP Confg0 will

appear in this bit.

This bit reflects a specific system configuration parame-

ter, as opposed to other devices, e.g., 8-bit data word

length.

Bit 7-4 - Reserved

These bits are reserved and are always 0001.

6.5.11

Configuration Register B (CNFGB), Bits 7-5 of

ECR = 111, Offset 401h

Configuration register B (CNFGB) is read only. Reading this

and DMA channel, and the state of the interrupt line.

Writing to this register has no effect and the data is ignored.

FIGURE 6-25. CNFGB Register Bitmap

76543210

Reset

Required

Configuration Register A

(CNFGA)

Offset 400h

Always 0

Bit 7 of PP Confg0

Bits 7-5 of ECR = 111

Always 0

Always 1

76543210

Reset

Required

Configuration Register B

(CNFGB)

Offset 401h

Reserved

Interrupt Select

IRQ Signal Value

Reserved

DMA Channel Select

Bits 7-5 of ECR = 111

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