PC97307 datasheet(124/218 Pages) NSC

124 / 218 page

124

Parallel Port (Logical Device 4)

www.national.com

Bits 1,0 - DMA Channel Select

These bits reflect the value of bits 1,0 of the PP Config0

tocol and ISA Interface Standard defines these bits as

shown in Table 6-7.

Bits 1,0 of PP Config0 are read/write bits, but CNFGB

bits are read only.

Upon reset, these bits are initialized to 00.

TABLE 6-7. ECP Mode DMA Selection

Bit 2 - Reserved

This bit is reserved and is always 0.

Bits 5-3 - Interrupt Select Bits

These bits reflect the value of bits 5-3 of the PP Config0

tocol and ISA Interface Standard defines these bits as

shown in Table 6-8.

Bits 5-3 of PP Config0 are read/write bits, but CNFGB

bits are read only.

Upon reset, these bits have undefined values.

TABLE 6-8. ECP Mode Interrupt Selection

Bit 6 - IRQ Signal Value

This bit holds the value of the IRQ signal configured by

the Interrupt Select register (index 70h of this logical de-

vice).

Bit 7 - Reserved

This bit is reserved and is always 0.

6.5.12

Extended Control Register (ECR), Offset 402h

This register controls the ECP and parallel port functions.

On reset this register is initialized to 00010101. IOCHRDY

is driven low on an ECR read when the ECR status bits do

not hold updated data.

Bit 1 Bit 0

DMA Conﬁguration

8-bit DMA selected by jumpers. (Default)

DMA channel 1 selected.

DMA channel 2 selected.

DMA channel 3 selected.

Bit 5

Bit 4

Bit 3

Interrupt Selection

Selected by jumpers.

IRQ7 selected.

IRQ9 selected.

IRQ10 selected.

IRQ11 selected.

IRQ14 selected.

IRQ15 selected.

IRQ5 selected.

FIGURE 6-26. ECR Register Bitmap

Bit 0 - FIFO Empty

This bit continuously reflects the FIFO state, and there-

fore can only be read. Data written to this bit is ignored.

When the ECP clock is frozen this bit is read as 1, re-

gardless of the actual FIFO state.

0 - The FIFO has at least one byte of data.

1 - The FIFO is empty or ECP clock is frozen.

Bit 1 - FIFO Full

This bit continuously reflects the FIFO state, and there-

fore can only be read. Data written to this bit is ignored.

When the ECP clock is frozen this bit is read as 1, re-

gardless of the actual FIFO state.

0 - The FIFO has at least one free byte.

1 - The FIFO is full or ECP clock frozen.

Bit 2 - ECP Interrupt Service

This bit enables servicing of interrupt requests. It is set

to 1 upon reset, and by the occurrence of interrupt

events. It is set to 0 by software.

While this bit is 1, neither the DMA nor the interrupt

events listed below will generate an interrupt.

While this bit is 0, the interrupt setup is “armed” and an

interrupt is generated on occurrence of an interrupt

event.

While the ECP clock is frozen, this bit always returns a

0 value, although it retains its proper value and may be

modified.

When one of the following interrupt events occurs while

this bit is 0, an interrupt is generated and this bit is set

to 1 by hardware.

— DMA is enabled (bit 3 of ECR is 1) and terminal

count is reached.

— FIFO write threshold reached (no DMA - bit 3 of ECR

is 0; forward direction (bit 5 of DCR is 0), and there

are eight or more bytes free in the FIFO).

— FIFO read threshold reached (no DMA - bit 3 of ECR

is 0; read direction set - bit 5 of DCR is 1, and there

are eight or more bytes to read from the FIFO).

0 - The DMA and the above interrupts are not disabled.

1 - The DMA and the above three interrupts are disabled.

76543210

Reset

Required

Extended Control

Offset 402h

ECP Interrupt Service

ECP Interrupt Mask

ECP Mode Control

ECP DMA Enable

FIFO Full

FIFO Empty

PC97307 датащи(PDF) 124 Page - National Semiconductor (TI)

PC97307 датащи(HTML) 124 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL