PC97307 datasheet(126/218 Pages) NSC

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126

Parallel Port (Logical Device 4)

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6.5.14

ECP Extended Data Register (EDR),

Offset 404h

This read/write register is the data port of the control regis-

ter indicated by the index stored in the EIR. Reading or writ-

ing this register reads or writes the data in the control

FIGURE 6-28. EDR Register Bitmap

Bits 7-0 - Data Bits

These read/write data bits transfer data to and from the

Control Register pointed at by the EIR register.

6.5.15

ECP Extended Auxiliary Status Register (EAR),

Offset 405h

Upon reset, this register is initialized to 00h.

FIGURE 6-29. EAR Register Bitmap

Bits 6-0 - Reserved

These bits are reserved.

Bit 7 - FIFO Tag

Read only. In mode 011, when bit 5 of the DCR is 1

(backward direction), this bit reflects the value of the tag

bit (BUSY status) of the word currently in the bottom of

the FIFO.

In other modes this bit is indeterminate.

76543210

Reset

Required

ECP Extended Data

Offset 404h

Data Bits

76543210

Reset

Required

ECP Extended Auxiliary

Offset 405h

Reserved

FIFO Tag

Status Register (EAR)

6.5.16

Control0, Second Level Offset 00h

Upon reset, this register is initialized to 00h.

FIGURE 6-30. Control0 Register Bitmap

Bit 0 - EPP Time-Out Interrupt Mask

0 - The EPP time-out is masked.

1 - The EPP time-out is generated.

Bit 3-1 - Reserved

This bit is reserved.

Bit 4 - Freeze Bit

In mode 011, setting this bit to 1 freezes part of the in-

terface with the peripheral device, and clearing this bit to

0 releases and initializes it.

In all other modes the value of this bit is ignored.

Bit 5 - DCR Register Live

When this bit is 1, reading the DCR (see 6.5.6 on page

122) reads the interface control lines pin values regard-

less of the mode selected.

Otherwise, reading the DCR reads the content of the

Bits 7, 6 - Reserved

This bit is reserved.

6.5.17

Control2, Second Level Offset 02h

Upon reset, this register is initialized to 00h.

FIGURE 6-31. Control2 Register Bitmap

76543210

Reset

Required

Control0 Register

Offset 00h

Reserved

EPP Time-Out

Reserved

Freeze Bit

DCR Register Live

Second Level

Interrupt Mask

76543210

Reset

Required

Control2 Register

Offset 02h

Revision 1.7 or 1.9 Select

Channel Address Enable

EPP 1.7 ZWS Control

Reserved

SPP Compatibility

Second Level

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