PC97307 datasheet(113/218 Pages) NSC

113 / 218 page

113

Parallel Port (Logical Device 4)

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In SPP Compatible mode, the parallel port does not write

data to the output signals. Bit 5 of the CTR register has no

effect in this state. If data is written (WR goes low), the data

is sent to the output signals PD7-0. If a read cycle is initiated

(RD goes low), the system reads the contents of the output

latch, and not data from the PD7-0 output signals.

In SPP Extended mode, the parallel port can read and write

external data via PD7-0. In this mode, bit 5 sets the direction

for data in or data out, while read or write cycles are possi-

ble in both settings of bit 5.

If bit 5 of CTR is cleared to 0, data is written to the output

signals PD7-0 when a write cycle occurs. (if a read cycle oc-

curs in this setting, the system reads the output latch, not

data from PD7-0).

If bit 5 of CTR is set to 1, data is read from the output signals

PD7-0 when a read cycle occurs. A write cycle in this setting

only writes to the output latch, not to the output signals PD7-

The reset value of this register is 0.

FIGURE 6-1. DTR Register Bitmap (SPP Mode)

SPP

Extended

Data written to PD7-0.

Data written is latched

Data read from output

latch.

Data read from PD7-0.

Mode

Bit 5 of

CTR

RD WR

Result

76543210

Reset

Required

SPP Data Register

(DTR)

Offset 00h

Data Bits

6.2.3

Status Register (STR), Offset 01h

This read-only register holds status information. A system

write operation to STR is an invalid operation that has no ef-

fect on the parallel port.

FIGURE 6-2. STR Register Bitmap (SPP Mode)

Bit 0 - Time-Out Status

In EPP modes only, this is the time-out status bit. In all

other modes this bit has no function and has the con-

stant value 1.

This bit is cleared when an EPP mode is enabled.

Thereafter, this bit is set to 1 when a time-out occurs in

an EPP cycle and is cleared when STR is read.

In EPP modes:

0 - An EPP mode is set. No time-out occurred since

STR was last read.

1 - Time-out occurred on EPP cycle (minimum of 10

µsec). (Default)

Bit 1 - Reserved

This bit is reserved and is always 1.

Bit 2 - IRQ Status

In all modes except SPP Extended, this bit is always 1.

In SPP Extended mode this bit is the IRQ status bit. It re-

mains high unless the interrupt request is enabled (bit 4 of

CTR set high). This bit is high except when latched low

when the ACK signal makes a low to high transition, indi-

cating a character is now being transferred to the printer.

Reading this bit resets it to 1.

0 - Interrupt requested in SPP Extended mode.

1 - No interrupt requested. (Default)

Bit 3 - ERR Status

This bit reflects the current state of the printer error sig-

nal, ERR. The printer sets this bit low when there is a

printer error.

0 - Printer error.

1 - No printer error.

Bit 4 - SLCT Status

This bit reflects the current state of the printer select sig-

nal, SLCT. The printer sets this bit high when it is on-line

and selected.

0 - No printer selected.

1 - Printer selected and online.

76543210

Reset

Required

SPP Status Register

(STR)

Offset 01h

IRQ Status

SLCT Status

PE Status

ACK Status

Printer Status

Time-Out Status

Reserved

ERR Status

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