PC97307 datasheet(117/218 Pages) NSC

117 / 218 page

117

Parallel Port (Logical Device 4)

www.national.com

6.3.9

EPP Data Register 3 (DATA3), Offset 07h

This is the fourth EPP data register. It is only accessed to

transfer bits 31 through 24 of a 32-bit read or write to EPP

Data Register 0 (DATA0).

FIGURE 6-11. EPP DATA3 Register Bitmap

6.3.10

EPP Mode Transfer Operations

The EPP transfer operations are address read or write, and

data read or write. An EPP transfer is composed of a sys-

tem read or write cycle from or to an EPP register, and an

EPP read or write cycle from a peripheral device to an EPP

EPP 1.7 Address Write

The following procedure selects a peripheral device or reg-

ister as illustrated in Figure 6-12.

1. The system writes a byte to the EPP Address register.

WR becomes low to latch D7-0 into the EPP Address

PD7-0 and the EPP pulls WRITE low.

2. The EPP pulls ASTRB low to indicate that data was

sent.

3. If WAIT was low during the system write cycle,

IOCHRDY becomes low. When WAIT becomes high,

the EPP pulls IOCHRDY high.

4. When IOCHRDY becomes high, it causes WR to be-

come high. If WAIT is high during the system write cycle,

then the EPP does not pull IOCHRDY to low.

5. When WR becomes high, it causes the EPP to pull first

ASTRB and then WRITE to high. The EPP can change

PD7-0 only when WRITE and ASTRB are both high.

76543210

Reset

Required

EPP Data Register 3

(DATA3)

Offset 07h

D26

D28

D29

D30

D31

D24

D25

D27

EPP Device

Read or Write Data

FIGURE 6-12. EPP 1.7 Address Write

EPP 1.7 Address Read

The following procedure reads from the EPP Address reg-

ister as shown in Figure 6-13.

1. The system reads a byte from the EPP Address register.

RD goes low to gate PD7-0 into D7-0.

2. The EPP pulls ASTRB low to signal the peripheral to

start sending data.

3. If WAIT is low during the system read cycle. Then the

EPP pulls IOCHRDY low. When WAIT becomes high,

the EPP stops pulling IOCHRDY to low.

4. When IOCHRDY becomes high, it causes RD to be-

come high. If WAIT is high during the system read cycle

then the EPP does not pull IOCHRDY to low.

5. When RD becomes high, it causes the EPP to pull

ASTRB high. The EPP can change PD7-0 only when

ASTRB is high. After ASTRB becomes high, the EPP

puts D7-0 in TRI-STATE.

FIGURE 6-13. EPP 1.7 Address Read

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

ZWS

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

ZWS

PC97307 датащи(PDF) 117 Page - National Semiconductor (TI)

PC97307 датащи(HTML) 117 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL