PC97307 datasheet(109/218 Pages) NSC

109 / 218 page

109

www.national.com

• Overrun error. The Overrun bit (bit 4) in ST1 is set. The

Interrupt Code (IC) bits (bits 7,6) in ST0 are set to abnor-

mal termination (01). If the microprocessor cannot ser-

vice a transfer request in time, the last correctly written

byte is written to the disk.

If the Multi-Track (MT) bit was set in the opcode command

byte, and the last sector of side 0 has been transferred, the

controller continues with side 1.

Result Phase

Upon terminating the execution phase of the WRITE DATA

command, the controller asserts IRQ6, indicating the begin-

ning of the result phase. The microprocessor must then

read the result bytes from the FIFO.

The values that are read back in the result bytes are shown

in Table 5-18 on page 98. If an error occurs, the result bytes

indicate the sector read when the error occurred.

5.7.25

The WRITE DELETED DATA Command

The WRITE DELETED DATA command receives data from

the host and writes logical sectors containing a deleted data

Address Mark (AM) to the selected drive.

This command is identical to the WRITE DATA command,

except that a deleted data AM, instead of a normal data AM,

is written to the data field.

Command Phase

See the READ DATA command starting on page 96 and

WRITE DATA on page 108 for a description of these bytes.

76543210

Result Phase Status Register 0 (ST0)

Result Phase Status Register 1 (ST1)

Result Phase Status Register 2 (ST2)

Track Number

Head Number

Sector Number

Bytes-Per-Sector Code

76543210

MFM

001001

IPS

XXXX

DS1

DS0

Track Number

Head Number

Sector Number

Bytes-Per-Sector Code

End of Track (EOT) Sector Number

Bytes Between Sectors - Gap 3

Data Length (Obsolete)

Execution Phase

Data is transferred from the system to the controller in DMA

or non-DMA modes, and written to the disk. See “Execution

Phase” starting on page 78 for a description of these data

transfer modes.

Result Phase

Upon terminating the execution phase of the WRITE DATA

command, the controller asserts IRQ6, indicating the begin-

ning of the result phase. The microprocessor must then

read the result bytes from the FIFO.

The values that are read back in the result bytes are shown

in Table 5-18 on page 98. If an error occurs, the result bytes

indicate the sector read when the error occurred.

76543210

Result Phase Status Register 0 (ST0)

Result Phase Status Register 1 (ST1)

Result Phase Status Register 2 (ST2)

Track Number

Head Number

Sector Number

Bytes-Per-Sector Code

PC97307 датащи(PDF) 109 Page - National Semiconductor (TI)

PC97307 датащи(HTML) 109 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL