PC97307 datasheet(112/218 Pages) NSC

112 / 218 page

112

Parallel Port (Logical Device 4)

www.national.com

TABLE 6-1. Parallel Port Mode Selection

a. Section 2.7.1 on page 37 describes the bits of the SuperI/O Parallel Port conﬁguration register.

b. See Section 6.5.12 on page 124

c. Before modifying this bit, set bit 4 of the SuperI/O Parallel Port conﬁguration register at index F0h to 1.

d. Use bit 7 of the Control2 register at second level offset 2 of the parallel port to further specify compatibility. See

Section 6.5.17 on page 126.

Conﬁguration

Time

Operation Mode

SuperI/O Parallel Port

Conﬁguration Register

(Index F0h)a

Extended Control Register

(ECR) of the Parallel Port

(Offset 402h) b

Control2 Register

of the Parallel Port

(Offset 02h) c

7 6 5

Conﬁguration at

System

Initialization

(Static)

SPP Compatible

0 0 0

SPP Extended

0 0 1

EPP Revision 1.7

0 1 0

EPP Revision 1.9

0 1 1

Conﬁguration at

System

Initialization

with

Run-Time

Reconﬁguration

(Dynamic)

SPP Compatible

1 0 0

1 1 1

0 0 0

PP FIFO

0 1 0

SPP Extended

0 0 1

EPP Revision 1.7

1 1 1

1 0 0

EPP Revision 1.9

ECP(Default)

1 0 0

1 1 1

0 1 1

TABLE 6-2. Parallel Port Reset States

6.2.1

Standard Parallel Port (SPP) Modes Register

Set

In all Standard Parallel Port (SPP) modes, port operation is

controlled by the registers listed in Table 6-3.

All register bit assignments are compatible with the assign-

ments in existing SPP devices.

A single Data Register DTR is used for data input and out-

put (see Section 6.2.2). The direction of data flow is deter-

mined by the system setting in bit 5 of the Control Register

CTR.

Signal

Reset Control

State After Reset

SLIN

TRI-STATE

INIT

Zero

AFD

TRI-STATE

STB

TRI-STATE

IRQ5,7

TRI-STATE

TABLE 6-3. Standard Parallel Port (SPP) Registers

6.2.2

SPP Data Register (DTR), Offset 00h

This bidirectional data port transfers 8-bit data in the direc-

tion determined by bit 5 of SPP register CTR at offset 02h

and mode.

The read or write operation is activated by the system RD

and WR strobes.

Table 6-4 tabulates DTR register operation.

TABLE 6-4. SPP DTR Register Read and Write Modes

Offset

Name

Description

R/W

00h

DTR

Data

R/W

01h

STR

Status

02h

CTR

Control

R/W

03h

TRI-STATE

Mode

Bit 5 of

CTR

RD WR

Result

SPP

Compatible

Data written to PD7-0.

Data read from the

output latch

PC97307 датащи(PDF) 112 Page - National Semiconductor (TI)

PC97307 датащи(HTML) 112 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL