PC87306 datasheet(16/110 Pages) NSC

16 / 110 page

20 Configuration Registers

21 OVERVIEW

Eighteen registers constitute the Base Configuration Regis-

ter set and control the PC87306 setup In general these

registers control the enabling of major functions (FDC

UARTs parallel port pin functionalty etc) the IO address-

es of these functions and whether they power-down via

hardware control or not These registers are the Function

Enable Register (FER)

the Function Address Register

(FAR) the Power and Test Register (PTR) the Function

Control Register (FCR) the Printer Control Register (PCR)

the Keyboard and Real-Time Clock Control Register (KRR)

the Power Management Control Register (PMC) the Tape

UARTs and Parallel Port Register (TUP) the SuperIO Iden-

tification Register (SID) the Advanced SIO Configuration

(CS0LA) the Chip Select 0 High Address Register (CS0HA)

the Chip Select 0 Configuraton Register (CS0CF) the Chip

Select 1 Low Address Register (CS1LA) the Chip Select 1

High Address Register (CS1HA) the Chip Select 1 Configu-

ration Register (CS1CF) the Infrared Configuration Register

(IRC) the General Purpose IO Port Base Address Configu-

ration Register (GPBA) and the SuperIO Configuration

The FER FAR PTR KRR and SCF0 registers can be ac-

cessed via hardware or software During reset the PC87306

loads a set of default values selected by a hardware strap-

ping option into the FER FAR and PTR Configuration Reg-

isters The remaining 13 registers can only be accessed by

software

An index and data register pair are used to read and write

these registers Each Configuration Register is pointed to by

the value loaded into the Index Register The data to be

written into the Configuration Register is transferred via the

Data register A Configuration Register is read in a similar

way (ie by pointing to it via the Index Register and then

reading its contents via the Data Register)

Accessing the Configuration Registers in this way requires

only two system IO addresses Since that IO space is

shared by other devices the Index and Data Registers can

still be inadvertantly accessed To reduce the chances of an

inadvertant access a simple procedure (see Section 22)

has been developed

To maintain compatibility with other SuperIO chips register

bits with reserved values may not be altered Use a read-

modify-write procedure

22 SOFTWARE CONFIGURATION

If the system requires access to the Configuration Registers

after reset the following procedure must be used to change

data in the registers

1 Determine the PC87306 Index Register’s default location

Check the four possible locations (see Table 2-1) by

reading them twice The first byte is the ID byte 88h The

second byte read is always 00h but read after write al-

ways brings the value of the written byte Compare the

data read with the ID byte and then 00h A match occurs

at the correct location Note that the ID byte is only is-

sued from the Index Register during the first read after a

reset Subsequent reads return the value loaded into the

Index Register Bits 5 – 7 are reserved and always read 0

2 Load the Configuration Registers

A Disable CPU interrupts

B Write the index of the Configuration Register (00h –

0Dh) to the Index Register one time

C Write the correct data for the Configuration Register in

two consecutive write accesses to the Data Register

D Enable CPU interrupts

3 Load the Configuration Registers (read-modify-write)

A Disable CPU interrupts

B Write the index of the Configuration Register (00h –

0Dh) to the Index Register one time

C Read the configuration data in that register via the

Data Register

D Modify the configuration data

E Write the changed data for the Configuration Register

in two consecutive writes to the Data Register The

F Enable CPU interrupts

A single read access to the Index and Data Registers can

be done at any time without disabling CPU interrupts When

the Index Register is read the last value loaded into the

Index Register is returned When the Data Register is read

the Configuration Register data pointed to by the Index Reg-

ister is returned

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