PC87306 datasheet(67/110 Pages) NSC

67 / 110 page

60 Serial Ports (Continued)

FCR Bits

RCVR FIFO

Trigger Level (Bytes)

FIGURE 6-2 Receiver FIFO Trigger Level

66 INTERRUPT IDENTIFICATION REGISTER (IIR)

In order to provide minimum software overhead during data

character transfers the UART prioritizes interrupts into four

levels and records these in the Interrupt Identification Reg-

ister The four levels of interrupt conditions in order of priori-

ty are Receiver Line Status Received Data Ready Trans-

mitter Holding Register Empty and MODEM Status

When the CPU accesses the IIR the UART freezes all inter-

rupts and indicates the highest priority pending interrupt to

the CPU While this CPU access is occurring the UART

records new interrupts but does not change its current indi-

cation until the current access is complete Table 6-2 shows

the contents of the IIR Details on each bit follow

Bit 0

This bit can be used in an interrupt environment to

indicate whether an interrupt condition is pending

When it is 0 an interrupt is pending and the IIR

contents may be used as a pointer to the appropri-

ate interrupt service routine When it is 1 no inter-

rupt is pending See Table 6-5

Bits 1 2

These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated in

Table 6-5

Bit 3

In the 16450 mode this bit is 0 In the FIFO mode it

is set along with bit 2 when a time-out interrupt is

pending See Table 6-5

Bits 4 5

These bits of the IIR are always 0

Bits 6 7

These two bits are set when FCR0 e 1 (FIFO

Mode enabled)

67 INTERRUPT ENABLE REGISTER (IER)

This register enables the five types of UART interrupts

Each interrupt can individually activate the appropriate inter-

rupt (IRQ3 or IRQ4) output signal It is possible to totally

disable the interrupt system by resetting bits 0 through 3 of

the Interrupt Enable Register (IER) Similarly setting bits of

this register to 1 enables the selected interrupt(s) Disabling

an interrupt prevents it from being indicated as active in the

IIR and from activating the interrupt output signal All other

system functions operate in their normal manner including

the setting of the Line Status and MODEM Status Registers

Table 6-2 shows the contents of the IER Details on each bit

follow See MODEM Control Register bit 3 for more informa-

tion on enabling the interrupt pin

Bit 0

When set to 1 this bit enables the Received Data

Available Interrupt and Timeout Interrupt in the

FIFO Mode

Bit 1

This bit enables the Transmitter Holding Register

Empty Interrupt when set to 1

Bit 2

This bit enables the Receiver Line Status Interrupt

when set to logic 1

Bit 3

This bit enables the MODEM Status Interrupt

when set to logic 1

Bits 4 – 7

These four bits are always logic 0

68 MODEM CONTROL REGISTER (MCR)

This register controls the interface with the MODEM or data

set (or a peripheral device emulating a MODEM) The con-

tents of the MODEM Control Register (MCR) are indicated

in Table 6-2 and are described as follows

Bit 0

This bit controls the Data Terminal Ready (DTR)

output When it is set to 1 the DTR output is

forced to a logic 0 When it is reset to 0 the DTR

output is forced to 1 In Local Loopback Mode this

bit controls bit 5 of the MODEM Status Register

Note

The DTR and RTS output of the UART may be applied to

an EIA inverting line driver (such as the DS1488) to ob-

tain the proper polarity input at the MODEM or data set

Bit 1

This bit controls the Request to Send (RTS) out-

put Its effect on the RTS output is identical to that

described above for bit 0 In Local Loopback

Mode

this bit controls bit 4 of the MODEM

Status Register

Bit 2

This bit is the OUT1 bit It does not have an output

pin associated with it It can be written to and read

by the CPU In Local Loopback Mode this bit con-

trols bit 6 of the MODEM Status Register

Bit 3

This bit enables the interrupt when set No exter-

nal pin is associated with this bit other than IRQ3

4 In Local Loopback Mode this bit controls bit 7

of the MODEM Status Register

Bit 4

This bit provides a Local loopback feature for diag-

nostic testing of the UART When it is set to 1 the

following changes take place the transmitter Seri-

al Output (SOUT) is set to the Marking (1) state

the receiver Serial Input (SIN) is disconnected the

output of the Transmitter Shift Register is ‘‘looped

back’’ (connected) to the Receiver Shift Register

the four MODEM Control inputs (DSR CTS RI

and DCD) are disconnected and the DTR RTS

OUT1 IRQ ENABLE bits in MCR are internally

connected to DSR CTS RI and DCD in MSR re-

spectively The MODEM Control output pins are

forced to their high (inactive) states In the Loop-

back Mode data that is transmitted is immediately

received This feature allows the processor to veri-

fy the transmit-and-received-data paths of the seri-

al port

In the Loopback Mode the receiver and transmit-

ter interrupts are fully operational The MODEM

Status Interrupts are also operational but the in-

terrupts’ sources are the lower four bits of MCR

instead of the four MODEM control inputs Writing

a 1 to any of these 4 MCR bits will cause an inter-

rupt In Loopback Mode the interrupts are still con-

trolled by the Interrupt Enable Register The IRQ3

and IRQ4 pins will be at TRI-STATE in the Loop-

back Mode

Bits 5 – 7

These bits are permanently set to 0

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