 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
PC87306 датащи(PDF) 64 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87306 датащи(HTML) 64 Page - National Semiconductor (TI) |
|
|
64 / 110 page  60 Serial Ports (Continued) TABLE 6-2 PC87306 Register Summary for an Individual UART Channel Register Address No Bit A0–2e0 A0–2e0 A0–2e1 22 3 4 5 6 7 A0–2e0 A0–2e1 DLABe0 DLABe0 DLABe0 DLABe1 DLABe1 Receiver Transmitter Interrupt Register Enable Interrupt FIFO Register Control Line Register MODEM Control Register Status Line Register MODEM Status Register Scratch Pad Divisor Latch (LSB) Divisor (MSB) Latch Buffer Holding Ident Control Register Register Register Register (Read (Write (Read (Write Only) Only) Only) Only) RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM 0 Data Bit 0 Data Bit 0 Enable ‘‘0’’ if FIFO Word Data Data Delta Bit 0 Bit 0 Bit 8 (Note 1) Received Interrupt Enable Length Terminal Ready Clear Data Pending Select Ready (DR) to Send Available Bit 0 (DTR) Interrupt 1 Data Bit 1 Data Bit 1 Enable Interrupt RCVR Word Request Overrun Delta Bit 1 Bit 1 Bit 9 Transmitter ID FIFO Length to Send Error Data Holding Bit Reset Select (RTS) (OE) Set Register Bit 1 Ready Empty Interrupt 2 Data Bit 2 Data Bit 2 Enable Interrupt XMIT Number of Out 1 Parity Trailing Bit 2 Bit 2 Bit 10 Receiver ID FIFO Stop Bits Bit Error Edge Ring Line Status Bit Reset (Note 3) (PE) Indicator Interrupt 3 Data Bit 3 Data Bit 3 Enable Interrupt Reserved Parity IRQ Framing Delta Bit 3 Bit 3 Bit 11 MODEM ID Enable Enable Error Data Status Bit (FE) Carrier Interrupt (Note 2) Detect 4 Data Bit 4 Data Bit 4 0 0 Reserved Even Parity Loop Break Clear to Bit 4 Bit 4 Bit 12 Select Interrupt Send (BI) 5 Data Bit 5 Data Bit 5 0 0 Reserved Stick 0 Transmitter Data Bit 5 Bit 5 Bit 13 Parity Holding Set Register Ready (THRE) 6 Data Bit 6 Data Bit 6 0 FIFOs RCVR Set 0 Transmitter Ring Bit 6 Bit 6 Bit 14 Enabled Trigger Break Empty Indicator (Note 2) (LSB) (TEMT) 7 Data Bit 7 Data Bit 7 0 FIFOs RCVR Divisor 0 Error in Data Bit 7 Bit 7 Bit 15 Enabled Trigger Latch RCVR Carrier (Note 2) (MSB) Access Bit FIFO Detect (DLAB) (Note 2) Note 1 Bit 0 is the least significant bit It is the first bit serially transmitted or received Note 2 These bits are always 0 in the NS16450 Mode Note 3 This bit no longer has a pin associated with it 64 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
