PC87306 datasheet(31/110 Pages) NSC

31 / 110 page

30 FDC Register Description (Continued)

316 Data Rate Select Register (DSR)

Write Only

This write-only register is used to program the data rate

amount of write precompensation power-down mode and

software reset The data rate is programmed via the CCR

not the DSR for PC-AT and PS2 Model 30 and MicroChan-

nel applications Other applications can set the data rate in

the DSR The data rate of the floppy controller is deter-

mined by the most recent write to either the DSR or CCR

The DSR is unaffected by a software reset A hardware re-

set sets the DSR to 02h which corresponds to the default

precompensation setting and 250 kbps

DSR

DESC

LOW

PRE-

DRATE1 DRATE0

RESET POWER

COMP2 COMP1 COMP0

RESET

COND

Software Reset

This bit has the same function as

the DOR RESET (D2) except that this software re-

set is self-clearing

Low Power

A 1 to this bit puts the controller into

the Manual Low Power mode The oscillator and

data separator circuits are turned off Manual Low

Power can also be accessed via the Mode com-

mand The chip comes out of low power after a soft-

ware reset or access to the Data Register or Main

Status Register

Undefined

Should be set to 0

D4 – 2

Precompensation Select

These three bits select

the amount of write precompensation the floppy

controller uses on the WDATA disk interface output

Table 3-6 shows the amount of precompensation

used for each bit pattern In most cases the default

values (Table 3-7) can be used however alternate

values can be chosen for specific types of drives

and media Track 0 is the default starting track num-

ber for precompensation The starting track number

can be changed in the Configure command

TABLE 3-6 Write Precompensation Delays

Bits 4 3 2

Precompensation Delay

111

00 ns

001

417 ns

010

833 ns

011

1250 ns

100

1667 ns

101

2083 ns

110

2500 ns

000

DEFAULT

TABLE 3-7 Default Precompensation Delays

Data Rate

Precompensation Delay

1 Mbps

417 ns

500 kbps

1250 ns

300 kbps

1250 ns

250 kbps

1250 ns

D1 0

Data Rate Select 10

These bits determine the

data rate for the floppy controller See Table 3-8 for

the corresponding data rate for each value of D1

D0 The data rate select bits are unaffected by a

software reset and are set to 250 kbps after a hard-

ware reset

TABLE 3-8 Data Rate Select Encoding

Data Rate Select

Data Rate

MFM

1 Mbps

Illegal

500 kbps

250 kbps

300 kbps

150 kbps

250 kbps

125 kbps

Note

FM mode is not guaranteed by functional testing

317 Data Register (FIFO)

ReadWrite

The FIFO (readwrite) is used to transfer all commands

data and status between the mP and the FDC During the

Command Phase the mP writes the command bytes into the

FIFO after polling the RQM and DIO bits in the MSR During

the Result Phase the mP reads the result bytes from the

FIFO after polling the RQM and DIO bits in the MSR

Enabling the FIFO and setting the FIFO threshold is done

via the Configure command If the FIFO is enabled only the

Execution Phase byte transfers use the 16 byte FIFO The

FIFO is always disabled during the Command and Result

Phases of a controller operation A software reset will not

disable enabled FIFO if the LOCK bit is set in the Lock

Command After a hardware reset the FIFO is disabled to

maintain compatibility with PC-AT systems

The 16-byte FIFO can be used for DMA Interrupt or soft-

ware polling type transfers during the execution of a read

write format or scan command In addition the FIFO can

be put into a Burst or Non-Burst mode with the Mode com-

mand In the Burst mode FDRQ or IRQ6 remains active

until all of the bytes have been transferred to or from the

FIFO In the Non-Burst mode FDRQ or IRQ6 is deasserted

for 350 ns to allow higher priority transfer requests to be

serviced The Mode command can also disable the FIFO for

either reads or writes separately The FIFO allows the sys-

tem a larger latency without causing a disk over-

rununderrun error The FIFO is typically used with multi-

tasking operating systems andor when running systems at

or above a 1 Mbps data rate In its default state the FIFO is

disabled and contains a zero threshold The default state is

entered after a hardware reset

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