PC87306 datasheet(57/110 Pages) NSC

57 / 110 page

50 FDC Functional Description (Continued)

software polling mode The last two modes are called the

Non-DMA modes The DMA mode is used if the system has

a DMA controller This allows the mP to do other tasks while

the data transfer takes place during the Execution Phase If

the Non-DMA mode is used an interrupt is issued for each

byte transferred during the Execution Phase Also instead

of using the interrupt during Non-DMA mode the Main

Status Register can be polled by software to indicate when

a byte transfer is required All of these data transfer modes

work with the FIFO enabled or disabled

5321 DMA ModeFIFO Disabled

The DMA mode is selected by writinga0tothe DMA bit in

the Specify command and by setting the DMA enabled bit

(D3) in the DOR With the FIFO disabled a DMA request

(DRQ) is generated in the Execution Phase when each byte

is ready to be transferred The DMA controller should re-

spond to the DRQ with a DMA acknowledge (DACK) and a

read or write strobe The DRQ is cleared by the leading

edge of the active low DACK input signal After the last byte

is transferred an interrupt is generated indicating the begin-

ning of the Result Phase During DMA operations the chip

select input (CS) must be held high The DACK signal acts

as the chip select for the FIFO in this case and the state of

the address lines A2 – A0 is a don’t care The Terminal

Count (TC) signal can be asserted by the DMA controller to

terminate the data transfer at any time Due to internal gat-

ing TC is only recognized when DACK is low

PC-AT Mode

When in the PC-AT interface mode with the

FIFO disabled the controller is in single byte transfer mode

That is the system has one byte time to service a DMA

request (DRQ) from the controller DRQ will be deasserted

between each byte

PS2 Mode

When in the PS2 mode DMA transfers with

the FIFO disabled are performed differently Instead of a

single byte transfer mode the FIFO is actually enabled with

THRESH e 0Fh Thus DRQ is asserted when one byte has

entered the FIFO during reads and when one byte can be

written to the FIFO during writes DRQ is deasserted by the

leading edge of the DACK input and is reasserted when

DACK goes inactive high This operation is very similar to

Burst mode transfer with the FIFO enabled except that DRQ

is deasserted between each byte

5322 DMA ModeFIFO Enabled

Read Data Transfers

Whenever the number of bytes in the FIFO is greater than

or equal to (16 b THRESH) a DRQ is generated This is the

trigger condition for the FIFO read data transfers from the

floppy controller to the mP

Burst Mode

DRQ remains active until enough bytes have

been read from the controller to empty the FIFO

Non-Burst Mode

DRQ is deasserted after each read trans-

fer If the FIFO is not completely empty DRQ is reasserted

after a 350 ns delay This allows other higher priority DMA

transfers to take place between floppy transfers In addition

this mode allows the controller to work correctly in systems

where the DMA controller is put into a read verify mode

where only DACK signals are sent to the FDC with no RD

pulses This read verify mode of the DMA controller is used

in some PC software The FIFO Non-Burst mode allows the

DACK input from the DMA controller to be strobed which

correctly clocks data from the FIFO

For both the Burst and Non-Burst modes when the last byte

in the FIFO has been read DRQ goes inactive DRQ is then

reasserted when the FIFO trigger condition is satisfied After

the last byte of a sector has been read from the disk DRQ

is again generated even if the FIFO has not yet reached its

threshold trigger condition This guarantees that all the cur-

rent sector bytes are read from the FIFO before the next

sector byte transfer begins

Write Data Transfers

Whenever the number of bytes in the FIFO is less than or

equal to THRESH a DRQ is generated This is the trigger

condition for the FIFO write data transfers from the mPto

the floppy controller

Burst Mode

DRQ remains active until enough bytes have

been written to the controller to completely fill the FIFO

Non-Burst Mode

DRQ is deasserted after each write

transfer If the FIFO is not full DRQ is reasserted after a 350

ns delay This deassertion of DRQ allows other higher priori-

ty DMA transfers to take place between floppy transfers

The FIFO has a byte counter which monitors the number of

bytes being transferred to the FIFO during write operations

for both Burst and Non-Burst modes When the last byte of

a sector is transferred to the FIFO DRQ is deasserted even

if the FIFO has not been completely filled Thus the FIFO is

cleared after each sector is written Only after the floppy

controller has determined that another sector is to be writ-

ten is DRQ asserted again Also since DRQ is deasserted

immediately after the last byte of a sector is written to the

FIFO the system does not need to tolerate any DRQ deas-

sertion delay and is free to do other work

Read and Write Data Transfers

The DACK input signal from the DMA controller may be held

active during an entire burst or it may be strobed for each

byte transferred during a read or write operation When in

the Burst mode the floppy controller deasserts DRQ as

soon as it recognizes that the last byte of a burst was trans-

ferred If DACK is strobed for each byte the leading edge of

this strobe is used to deassert DRQ If DACK is strobed RD

or WR are not required This is the case during the Read-

Verify mode of the DMA controller If DACK is held active

during the entire burst the trailing edge of the RD or WR

strobe is used to deassert DRQ DRQ is deasserted within

50 ns of the leading edge of DACK RD orWR This quick

response should prevent the DMA controller from transfer-

ring extra bytes in most applications

Overrun Errors

An overrun or underrun error terminates the execution of

the command if the system does not transfer data within the

allotted data transfer time (see Section 37) which puts the

controller into the Result Phase During a read overrun the

P is required to read the remaining bytes of the sector

before the controller asserts IRQ6 signifying the end of ex-

ecution During a write operation an underrun error termi-

nates the Execution Phase after the controller has written

the remaining bytes of the sector with the last correctly writ-

ten byte to the FIFO and generated the CRC bytes Whether

there is an error or not an interrupt is generated at the end

of the Execution Phase and is cleared by reading the first

Result Phase byte

PC87306 датащи(PDF) 57 Page - National Semiconductor (TI)

PC87306 датащи(HTML) 57 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL