PC87306 datasheet(70/110 Pages) NSC

70 / 110 page

80 Parallel Port

81 INTRODUCTION

This parallel interface is designed to provide all of the sig-

nals and registers needed to communicate through a stan-

dard parallel printer port as found in the IBM PC-XT PC-AT

PS2 and Centronics systems This parallel port supports

three standard modes of operation SPP EPP ECP The

Standard Parallel Port (SPP) is a software based protocol

with performance of up to 150 kbps

The Enhanced Parallel Port (EPP) is a hardware protocol

which offers up to 2 Mbps

The Extended Capabilities Port (ECP) is also a hardware

protocol with up to 2 Mbps transfer rate In addition the

ECP has FIFO’s for receive and transmit and DMA support

to reduce the CPU overhead The ECP mode 0 is in fact

compatible with the SPP mode The ECP specification de-

fines the ACDC parameters of the signals to allow fast

communication without termination problems

All the above standards are incorporated into the 1284 IEEE

specifications

The address decoding of the registers in SPP mode utilizes

A0 and A1 as shown in Table 8-1 (Address decoding of

registers in EPP and ECP modes is shown in Table 8-5 and

8-7 respectively) Table 8-3 shows the Reset states of Par-

allel port registers and pin signals These registers are

shown in Section 82 to Section 84

TABLE 8-1 Parallel Interface Register Addresses

Address

Access

Data

ReadWrite

Status

Read

Control

ReadWrite

TRI-STATE

Special circuitry provides protection against damage that

might be caused when the printer is powered but the

PC87306 is not

There are two Standard Parallel Port (SPP) modes of opera-

tion (Compatible and Extended see Table 8-2) two En-

hanced Parallel Port (EPP) modes of operation and one Ex-

tended Capabilities Port (ECP) mode to complete a full IEEE

1284 parallel port

TABLE 8-2 Standard Parallel Port

Modes Selection

Port Function

PTR7

Compatible

Extended

In Compatible mode a write operation causes the data to be

presented on pins PD0 – PD7 A read operation in this mode

causes the Data Register to present the last data written to

it by the CPU See Table 8-3

In the Extended Mode a write operation to the data register

causes the data to be latched If the Data Port Direction bit

(CTR5) is 0 the latched data is presented to the pins if it is

1 the data is only latched When Data Port Direction bit

(CTR5) is 0 a read operation from this register allows the

CPU to read the last data it wrote to the port In the Extend-

ed Mode with the Data Port Direction bit set to 1 (read) a

read from this register causes the port to present the data

on pins PD0 – PD7

TABLE 8-3 SPP Data Register Read and Write Modes

PTR7

CTR5

Result

Data Written to PD0 – 7

Data Read from the Output

Latch

Data Written to PD0 – 7

Data Written is Latched

Data Read from the Output

Latch

Data Read from PD0 – 7

To support a high transfer rate the IO buffers of the paral-

lel port signals require improved impedance matching IEEE

P1284 defines two types of IO buffers Level 1 (standard

IO buffersopen-drain with weak pull-up) and Level 2

(new IO bufferspush-pull with driver impedance and slew

rate according to new standards)

IEEE P1284 Draft 200 September 10 1993 Microsoft’s

ECP Protocol and ISA Interface Standard revision 114

July 7 1993 provide detailed descriptions of Level 2 IO

buffers

When in EPP 19 or ECP mode 3 or ECP mode 2 with bit 1

of PCR equal to 1 the following parallel port pins have Level

2 IO buffers PD0 – PD7 STB AFD INIT SLIN ACK ERR

SLCT PE and BUSY

(See DC Electrical Characteristics Section 111 for further

information)

82 DATA REGISTER (DTR)

TLC12379 – 39

This is a bidirectional data port that transfers 8-bit date The

direction is determined by the PTR7 and the CTR5 bits

When PTR7 is high the CTR5 bit will determine the data

direction in conjunction with the Read and Write strobes

When PTR7 bit is low the parallel port operates in the out-

put mode only See PTR7 bit and CTR5 bit for further infor-

mation The reset value of this register is 0 See Table 8-3

83 STATUS REGISTER (STR)

TLC12379 – 40

This register provides status for the signals listed below It is

a read only register Writing to it is an invalid operation that

has no effect

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