PC87306 datasheet(77/110 Pages) NSC

77 / 110 page

80 Parallel Port (Continued)

The FIFO does not stall when overwritten or underrun (ac-

cess is ignored) Bytes are always read from the top of the

FIFO regardless of the direction bit (bit 5 of DCR) For ex-

ample if 44h 33h 22h 11h is written into the FIFO reading

the FIFO returns 44h 33h 22h 11h (in the same order it

was written)

CNFGA

Configuration Register A Read only

Reading this register always returns 0001x100 Writing this

Bit 3 of CNFGA reflects the value of bit 5 of the ASC regis-

ter

CNFGB

Configuration Register B Read only

Reading this register returns the configured parallel port in-

terrupt line and its state as follows

Bit 7

This bit is always 0

Bit 6

Holds the (non-inverted) value on the config-

ured IRQ pin

Bits 5 4

These bits are 1 when IRQ5 is configured and

0 when IRQ7 is configured

Bit 3

This bit is always 1

Bit 2

This bit is always 0

Writing this register has no effect and the data

is ignored

Bits 1 0

These bits reflect the values of bit 2 and 1 re-

spectively of the SCF1 register

ECR

Extended Control Register This register controls the

ECP and parallel port functions Upon reset this register is

initialized to 00010101

IOCHRDY is driven low on ECR read when the ECR status

bits are not holding updated data

Bits 7 – 5

(Mode) Bit 7 is the MSB of the three bits value

000 Standard mode

Write cycles are per-

formed under software control STB AFD

INIT and SLIN are open-drain outputs

Bit 5 of DCR is ignored (assumes forward

direction) and PD0 – PD7 are driven The

FIFO is reset (empty)

001 PS2 mode Read and write cycles are

performed under software control The

FIFO is reset (empty) STB AFD INIT

and SLIN are open-drain outputs

010 Parallel Port FIF0 mode Write cycles are

performed under hardware control (STB is

controlled by hardware) Bit 5 of DCR is

ignored (assumes forward direction) and

PD0 – PD7 are driven STB AFD INIT and

SLIN are open-drain output buffers when

bit 1 of PCR is 0 When bit 1 of PCR is 1

the output buffers are push-pull

011 ECP FIFO mode The FIFO direction is

controlled by bit 5 of DCR

Read and write cycles to the device are

performed under hardware control (STB

and AFD are controlled by hardware)

STB AFD INIT and SLIN are push-pull

output buffers

100 Reserved

101 Reserved

110 FIFO test mode The FIFO is accessible

via the TFIFO register

The ECP does not issue ECP cycles to fill

empty the FIFO

111 Configuration mode

The CNFGA and

CNFGB registers are accessible in this

mode

Bit 4

ECP Interrupt Mask bit When this bit is 0 an

interrupt is generated on ERR assertion (the

high-to-low edge of ERR) An interrupt is also

generated when ERR is asserted while this bit is

changed from 1 to 0 this prevents the loss of

an interrupt between ECR read and ECR write

When this bit is 1 no interrupt is generated

Bit 3

ECP DMA Enable bit When this bit is 0 DMA is

disabled and the PDRQ pin is in TRI-STATE

When this bit is 1 DMA is enabled and DMA

starts when bit 2 of ECR is 0

Note

PDACK is assumed inactive when this bit is 0

Bit 2

ECP Service bit When this bit is 0 and one of

the following three interrupt events occur an in-

terrupt is generated and this bit is set to 1 by

hardware

1 Bit 3 of ECR is 1 and terminal count is

reached during DMA

2 Bit 3 of ECR is 0 and bit 5 of DCR is 0 and

there are eight or more bytes free in the

FIFO

3 Bit 3 of ECR is 0 and bit 5 of DCR is 1 and

there are eight or more bytes to be read from

the FIFO

When this bit is 1 DMA and the above three

interrupts are disabled

Writing 1 to this bit does not cause an interrupt

When the ECP clock is frozen this bit is read as

0 regardless of its actual value (even though

the bit may be modified by software when the

ECP clock is frozen)

Bit 1

FIFO Full bit Read only

This bit is 0 when the FIFO has at least one free

byte

This bit is 1 when the FIFO is full

This bit continuously reflects the FIFO state

and therefore can only be read Data written to

this bit is ignored

When the ECP clock is frozen this bit is read as

1 regardless of the actual FIFO state

Bit 0

FIFO Empty bit Read only

This bit is 0 when the FiFO has at least one byte

of data

This bit is 1 when the FIFO is empty

This bit continuously reflects the FIFO state

and therefore can only be read Data written to

this bit is ignored

When the ECP clock is frozen this bit is read as

1 regardless of the actual FIFO state

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