PC87306 datasheet(88/110 Pages) NSC

88 / 110 page

100 Keyboard Controller and Real-Time Clock (Continued)

TLC12379 – 59

where

UIP eUpdate In Progress Bit

UF e Update Ended Flag (Update Ended Interrupt if Enabled)

PF e Periodic Flag (Periodic Interrupt if Enabled)

AF e Alarm Flag (Alarm Interrupt if Enabled)

Flags (and IRQ) are reset at the conclusion of Control Register C read or by RESETC low

A e

Update in Progress Bit High before Update Occurs e 244 ms

B e

Periodic interrupt to Update e P2 a 244 ms

C e

Update to Alarm Interrupt e 305 ms

P e

Period is programmed by RS3–0 of control Register A

FIGURE 10-14 InterruptStatus Timing

The update occurs 244 ms after the update-in-progress

bit goes high Therefore ifa0is read there is a minimum

of 244 ms in which the time is guaranteed to remain sta-

ble

Method 4

Use a Periodic interrupt to determine if an

update cycle is in progress

The periodic interrupt is first set to a desired period The

program can then use the periodic interrupt to signify that

there is (Periodic Interrupt2 a 244 ms) remaining until

another update occurs

The Alarm condition is also generated by the Time Keeping

function After each update the seconds minutes and

hours are compared with the seconds alarm minutes alarm

and hours alarm If equal the Alarm lag is set in Control

the Alarm Interrupt Enable bit is set in Control Register B If

both bit 7 and bit 6 of any alarm byte (seconds alarm min-

utes alarm hours alarm) are 1 then that alarm byte is a

‘‘don’t care’’

1025 RAM

The RAM data is accessed at locations 0E – 7F when

RAMSEL (bit 2) of the configuration registers is 0 and loca-

tions 00 – 7F when RAMSEL is 1 Battery backed power en-

ables the RAM to retain information during system power-

down

Bit 0 of SCF0 locks RTC RAM cells at addresses 38-3Fh

The bit is 0 upon reset thus enabling read and write access

When the bit is 1 writes to RTC RAM cells at addresses

38 – 3Fh are ignored and reads return FFh Once set to 1

the bit can only be cleared by a hardware reset

1026 Power Management

The Power Management function provides power to the

RTC in the PC87306 During system operation power from

the system is used When system voltage falls below battery

voltage the Power Management function switches the RTC

cell to battery power For proper operation a 500 mV differ-

ential is needed between VCC and VBAT Figure 10-15 rep-

resents a typical battery configuration and

Figure 10-16 rep-

resents typical battery current during battery backed mode

TLC12379 – 60

FIGURE 10-15 Typical Battery Configuration

TLC12379 – 61

FIGURE 10-16 Typical Battery Current

during Battery Backed Mode

PC87306 датащи(PDF) 88 Page - National Semiconductor (TI)

PC87306 датащи(HTML) 88 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL