PC87306 datasheet(28/110 Pages) NSC

28 / 110 page

30 FDC Register Description (Continued)

The FDC has internal 24 mA data bus buffers which allow

direct connection to the system bus The internal 40 mA

totem-pole disk interface buffers are compatible with both

CMOS drive inputs and 150X resistor terminated disk drive

inputs

31 FDC CONTROL REGISTERS

The following FDC registers are mapped into the addresses

shown in Table 3-1 and described in the following sections

The base address range is provided by the on-chip address

decoder pin For PC-AT or PS2 applications the diskette

controller primary address range is 3F0 to 3F7h and the

secondary address range is 370 to 377h The FDC supports

three different register modes the PC-AT mode PS2

mode (Micro Channel systems) and the Model 30 mode

(Model 30) See Section 52 for more details on how each

nition for each mode of operation is given If no special

notes are made then the register is valid for all three regis-

ter modes

TABLE 3-1 Register Description and Addresses

A1 A0

IDENT

Status Register A

SRA

Status Register B

SRB

RW Digital Output Register

DOR

RW Tape Drive Register

TDR

Main Status Register

MSR

Data Rate Select Register

DSR

RW Data Register (FIFO)

FIFO

None (Bus TRI-STATE)

Digital Input Register

DIR

Configuration Control Register

CCR

Note

SRA and SRB are enabled by IDENT e 0 during a chip reset only

311 Status Register A (SRA)

Read Only

This is a read-only diagnostic register that is part of the

PS2 floppy controller register set and is enabled when in

the PS2 mode This register monitors the state of the IRQ6

pin and some of the disk interface signals The SRA can be

read at any time when in PS2 mode In the PC-AT mode

D7 – D0 are TRI-STATE during a mP read

SRAPS2 Mode

DESC

IRQ6

RES

STEP

TRK0

HDSEL

INDX

DIR

PEND

RESET

COND

Interrupt Pending

This active high bit reflects the

state of the IRQ6 pin

Reserved

Step

Active high status of the STEP disk interface

output

Track 0

Active low status of the TRK0 disk inter-

face input

Head Select

Active high status of the HDSEL disk

interface output

Index

Active low status of the INDEX disk interface

input

Write Protect

Active low status of the WP disk in-

terface input

Direction

Active high status of the DIR disk inter-

face output

312 Status Register B (SRB)

Read Only

This read-only diagnostic register is part of the PS2 floppy

controller register set and is enabled when in the PS2

mode The SRB can be read at any time when in PS2

mode In the PC-AT mode D7 – D0 are TRI-STATE during a

P read

SRBPS2 Mode

DESC

DR0

WDATA

RDATA

WGATE

MTR1

MTR0

RESET

COND

Reserved

Always 1

Reserved

Always 1

Drive Select 0

Reflects the status of the Drive Se-

lect 0 bit in the DOR (address 2 bit 0) It is cleared

after a hardware reset not a software reset

Write Data

Every inactive edge transition of the

WDATA disk interface output causes this bit to

change states

Read Data

Every inactive edge transition of the

RDATA disk interface output causes this bit to

change states

Write Gate

Active high status of the WGATE disk

interface output

Motor Enable 1

Active high status of the MTR1

disk interface output Low after a hardware reset

unaffected by a software reset

Motor Enable 0

Active high status of the MTR0

disk interface output Low after a hardware reset

unaffected by a software reset

313 Digital Output Register (DOR)

ReadWrite

The DOR controls the drive select and motor enable disk

interface outputs enables the DMA logic and contains a

software reset bit The contents of the DOR is set to 00h

after a hardware reset and is unaffected by a software re-

set The DOR can be written to at any time

DOR

DESC

MTR3 MTR2 MTR1 MTR0 DMAEN RESET

DRIVE DRIVE

SEL 1

SEL 0

RESET

0000

COND

Motor Enable 3

This bit controls the MTR3 disk

interface output A1in this bit causes the MTR3 pin

to go active

Motor Enable 2

Same function as D7 except for

MTR2

Motor Enable 1

Same function as D7 except for

MTR1 (See bit 4 of FCR for further information)

Motor Enable 0

Same function as D7 except for

MTR0 (See bit 4 of FCR for further information)

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