PC87306 datasheet(84/110 Pages) NSC

84 / 110 page

100 Keyboard Controller and Real-Time Clock (Continued)

RAM locations 0h – 7h are used as register bank0 They are

designated as R0 – R7 respectively Register bank1 (R0 –

R7 ) are located in 18h – 1Fh of the address map Bank0 is

the default register bank when the chip comes out from re-

set Bank switching is accomplished by using ‘‘register bank

select’’ instructions (SEL RB0 SEL RB1) Locations 8h –

17h are reserved for the stack Each stack entry consists of

2 bytes

Figure 10-6 shows the organization of the stack

The stack pointer in the PSW register points to the top of

the stack A0inthe stack pointer corresponds to RAM

locations 8h and 9h

TLC12379 – 52

FIGURE 10-6 Keyboard Controller Stack Organization

Program Status Word Register (PSW)

This 8-bit register holds the program execution status The

bit definition of the PSW register is shown in

Figure 10-7

res

SP k20l

bit

2-0

FIGURE 10-7 PSW Register Bits

Bit 7

CY Carry flag of the accumulator

Bit 6

AC Auxiliary Carry flag of the accumulator ie

carry from bit 3 to 4 of the ALU

Bit 5

F0 Flag 0 A general purpose software flag

Bit 4

BS The current active register bank

0 e bank 0 1 e bank 1

Bit 3

Reserved User should not change its power-up

value

Bits 2-0

Stack Pointer 3-bit Stack Pointer for 8-level stack

When the CPU performs a subroutine call or interrupt call

the PC and the upper 4 bits of the PSW are pushed into the

stack Upon return the PSW can be restored in option If a

RETR Return instruction is executed PSW is restored PSW

is not restored if an RET Return instruction is executed See

Figure 10-6

1014 IO Interface

The keyboard controller of the PC87306 provides 16 gener-

al purpose IO lines two open-collector output lines and

two input lines as shown in the Functional Block Diagram in

Figure 10-1

General Purpose IO

The 16 general purpose IO lines P12 – P17 and P20 – P21

are mapped to Port 1 and Port 2 respectively These IO

lines are quasi-bidirectional because the output buffer can-

not be turned off even if the IO line is intended for input

Whena0is written to an IO line it behaves like an output

Whena1is written to an IO line it behaves like an input

On reset all IO lines are inputs

Figure 10-8 illustrates the structure of the IO line Q1 and

Q2 are the normal output transistors When the IO line is

intended for output 0 is written into the flip-flop which latch-

es and Q2 turns on When 1 is written Q1 turns on briefly

because it is gated by a short port-write pulse also Q1

charges up the pad to near VCC and then turns off An ac-

tive pull-up transistor Q3 turns on also but it provides a

large pull-up resistance because it is a weak transistor At

this stage the IO line can be used as input a low imped-

ance low voltage can override the pin and the input buffer

reads a low level input If the pin is driven high or undriven a

high level is read Therefore to use a port pin as input a

logic 1 must first be written to it When the keyboard control-

ler is reset all port lines will be initialized to logic 1

Because Q1 turns on momentarily when a write to the port

is performed there is potential for a current surge A series

resistor connected to those port lines used as inputs is rec-

ommended to limit the potential surge

(Figure 10-9)

TLC12379 – 54

FIGURE 10-8 Active Pull-Up IO Port Structure

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