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PC87306 датащи(PDF) 98 Page - National Semiconductor (TI) |
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PC87306 датащи(HTML) 98 Page - National Semiconductor (TI) |
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98 / 110 page ![]() 120 Electrical Characteristics (Continued) 1226 Receiver Timing Symbol Parameter Conditions Min Max Units tIRRXW IRRX Pulse Width 16 ms 616 BAUD OUT Cycles tRAI Delay from Active Edge of RD to Reset IRQ 78 ns tRINT Delay from Inactive Edge of RD (RD LSR) to Reset IRQ 55 ns tSCD Delay from RCLK to Sample Time (Note 1) 41 ns tSINT Delay from Stop Bit to Set Interrupt 2 Baud Out Cycles Note 1 This is an internal timing specification and is therefore not tested TLC12379 – 75 FIGURE 12-7 Receiver Timing TLC12379 – 76 Note 1 If SCR0 e 1 then tSINT e 3 RCLKs For a Timeout Interrupt tSINT e 8 RCLKs FIGURE 12-8 FIFO Mode Receiver Timing 98 |
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