PC87306 datasheet(27/110 Pages) NSC

27 / 110 page

20 Configuration Registers (Continued)

3 Clear PTR bit 1 and then set PTR bit 0 (power-down)

high See Section 253 PTR bits 0 and 1

27 POWER-UP PROCEDURE AND CONSIDERATIONS

271 UART Power-Up

The clock signal to the UARTs is controlled through the

Configuration Registers (FER PTR) In order to restore the

clock signal to one or both UARTs the following conditions

must exist

1 The appropriate enable bit (FER 12) for the UART(s)

must be set

2 and the power-down bit (PTR 0) must not be set

272 FDC Power-Up

The clock signal to the FDC is controlled through the Con-

figuration Registers the FDC Mode Command and the Data

Rate Select Register In order to restore the clock signal to

the FDC the following conditions must exist

1 The appropriate enable bit (FER 3) must be set

2 and the power-down bit (PTR 0) must not be set

In addition to these conditions one of the following must be

done to initiate the recovery from power-down mode

1 Read the Main Status Register until the RQM bit (MSR7)

is set or

2 Write to the Data Rate Select Register and set the Soft-

ware Reset bit (DSR7) or

3 Write to the Digital Output Register clear and then set

the Reset bit (DOR2) or

4 Read the Data Register and the Main Status Register

until the RQM bit is set

If the crystal has been stopped read the RQM bit in the

Main Status Register until it is set The RQM bit is not set

until the crystal has stabilized

30 FDC Register Description

The floppy disk controller is suitable for all PC-AT EISA

PS2 and general purpose applications The operational

mode (PC-AT PS2 and Model 30) of the FDC is deter-

mined by bits 7 6 of ASC register AT mode is the default

DP8473 and N82077 software compatibility is provided Key

features include a 16-byte FIFO PS2 diagnostic register

support perpendicular recording mode CMOS disk inter-

face and a high performance analog data separator See

Figure 3-1

The FDC supports the standard PC data rate drives of 250

500 kbps 300500 kbps and 1 Mbps in MFM-encoded data

mode but is no longer guaranteed through functional test-

ing to support the older FM encoded data mode Refer-

ences to the older FM mode remain in this document to

clarify the true functional operation of the device

The 1 Mbps data rate is used by the high performance tape

and floppy drives The FDC supports these floppy drives

which utilize high density media and require the perpendic-

ular recording mode format When used with the 1 Mbps

data rate this new format allows the use of 4 MB floppy

drives which format Extra Density (ED) media to 288 MB

capacity

The high performance internal analog data separator needs

no external components It improves on the window margin

performance standards of the DP8473 and is compatible

with the strict data separator requirements of floppy disk

and floppy-tape drives

The FDC contains write precompensation circuitry that de-

faults to 125 ns for 250 kbps 300 kbps and 500 kbps and

to 4167 ns for 1 Mbps These values can be overridden in

software to disable write precompensationn or to provide

levels of precompensation up to 250 ns

TLC12379 – 28

FIGURE 3-1 FDC Functional Block Diagram

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