PC87306 datasheet(25/110 Pages) NSC

25 / 110 page

20 Configuration Registers (Continued)

1 Half Duplex The receiver input is blocked to 1

while the transmitter is busy from the begin-

ning of the start bit till the end of the stop

bit(s)

Bits 2 – 3

Reserved

Bit 4

Encoded IR transmitter drive control bit

0 When IRTX is active it is active for 16 ms

1 When IRTX is active it is active for 316 baud

In Normal (MODEM) Mode and in Non Encoded

IR mode this bit is ignored

Bit 5

EncodedNon Encoded IR mode

0 Encoded Mode UART2’s SOUT is encoded

and routed to the IRTX pin and the IRRX pin is

decoded and routed to UART2’s SIN

1 Non Encoded Mode UART2’s SOUT is invert-

ed and routed to the IRTX pin and the IRRX is

routed to UART2’s SIN

In Normal (MODEM) Mode this bit is ignored

Bits 6 – 7

Reserved

2518 General Purpose IO Port Base Address

Configuration Register (GPBA Index e 0Fh)

This register holds address bits A2 – 9 of the GPIO Ports

base address Bit 0 holds A2

The other 8 bits of the 16-bit base address are 0 The base

address is therefore composed as follows

A15

A10

GPBA

GPIO Port 1 is at the base address and GPIO Port 2 at the

base address a 1

Upon reset GPBA is initialized to 00011110 thus dictating

base address e 78h

2519 SuperIO Configuration Register 0 (SCF0

Index e 12h)

See Table 2-1 for reset value

Bit 0

RTC RAM lock bit Once this bit is set to 1 it can

only be cleared by a hardware reset

0 Read and write access to locations 38 – 3Fh of

the RTC RAM is not blocked

1 Read and write access to locations 38 – 3Fh of

the RTC RAM is blocked Writes are ignored

and reads return FFh

Note that bit 7 of the PCR register also affects

RTC RAM locking even when this bit is 0

Bit 1

IRQ1 and IRQ12 latch enable

0 Hardware latching is disabled (8042 compati-

ble mode)

1 Hardware latching is enabled (IRQ latching

mode)

Bit 2

IRQ12 TRI-STATE control bit

0 IRQ12 is driven with quasi-bidirectional buffer

1 IRQ12 output is in TRI-STATE mode and

IRQ12 input is masked to 1

Bit 3

UART2 TRI-STATE control bit UART2 and IR

outputs except IRQ3 and IRQ4 pins are in TRI-

STATE and the inputs are blocked to reduce

their leakage current when this bit is 1 and either

UART2 is disabled or the PC87306 is in power-

down mode

See Section 7 for further information

Bit 4

General Purpose IO Port 1 (GPIO10 – 17) En-

able

0 GPIO Port 1 Disabled Accesses to GPIO Port

1 is ignored

1 GPIO Port 1 Enabled GPIO Port 1 responds to

non DMA read and write accesses

Bit 5

General Purpose IO Port 2 (GPIO20 – 27) En-

able

0 GPIO Port 2 Disabled Accesses to GPIO Port

2 is ignored

1 GPIO Port 2 Enabled GPIO Port 2 responds to

non DMA read and write accesses

Bit 6

Reserved

Bit 7

Reserved

Upon reset the non reserved bits of SCF0 are initialized to

either 0x000000 or 0x110000 according to the CFG1 strap

2520 SuperIO Configuration Register 1 (SCF1

Index e 18h)

Upon reset the implemented bits are initialized to 0

Bit 0

Reserved

Bits 1 2

Reported ECP DMA number as reflected on bits

0 and 1 of the CNFGB ECP register Bit 2 of

SCF1 is reflected on bit 1 of CNFGB and bit 1 of

SCF1 on bit 0 of CNFGB Microsoft’s ECP Proto-

col and ISA Interface Standard defines these bits

as follows (bit 1 of CNFGB is MSB)

00 Jumpered 8-bit DMA

01 DMA channel 1 selected

10 DMA channel 2 selected

11 DMA channel 3 selected

Bit 3

Selected ECP DMA pins

0 PDRQ0 and PDACK0 pins are used for ECP

DMA

1 PDRQ1 and PDACK1 pins are used for ECP

DMA

Note

(For bits 1–3) It is the (PnP BIOS) softwares responsi-

bility to match the DMA channel number as reflected in

the CNFGB register to the selected channel (for the

given wiring of those pins to the host DMA channel

pins) ie to match the value written in bits 2–1 to the

value of bit 3 according to the PC87306 wiring

Bits 4 5

Reserved

Bits 6 7

These bits are general purpose scratch bits

When bit 3 of the FCR is 0 the bits are read

write bits When bit 3 of the FCR is 1 the bits are

read-only After reset they are readwrite bits

Once the bits are changed to be read-only they

can be changed back to be readwrite bits only

by assertion of reset

2521 LPT Base Address Register (LPTBA Index e

19h)

This register holds address bits A2 – 9 of the parallel port

base address when LPTA is selected via bits 0 1 of FAR

ie when bit 1 of FAR is 0 and bit 0 of FAR is 1 Bit 0 of

LPTBA holds A2 The other eight bits of the 16-bit base

address (ie A0 – 1 and A10 – 15) are 0 The base address is

therefore composed as follows

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