PC87306 datasheet(65/110 Pages) NSC

65 / 110 page

60 Serial Ports (Continued)

TABLE 6-3 PC87306 UART Reset Configuration

Reset Control

Reset State

Interrupt Enable

Master Reset (MR)

0000

0000 (Note 1)

Interrupt Identification

Master Reset

0000 0001

FIFO Control

Master Reset

0000 0000

Line Control

Master Reset

0000 0000

MODEM Control

Master Reset

000

0 0000

Line Status

Master Reset

0110 0000

MODEM Status

Master Reset

XXXX 0000 (Note 2)

SOUT

Master Reset

High

INTR (RCVR Errs)

Read LSRMR

LowTRI-STATE

INTR (RCVR Data Ready)

Read RBRMR

LowTRI-STATE

INTR (THRE)

Read IIRWrite THRMR

LowLowTRI-STATE

INTR (Modem Status Changes)

Read MSRMR

LowTRI-STATE

Interrupt Enable Bit

Master Reset

Low

RTS

Master Reset

High

DTR

Master Reset

High

RCVR FIFO

MR or (FCR1e1 and FCR0e1) or Change in FCR0

All Bits Low

XMIT FIFO

MR or (FCR2e1 and FCR0e1) or Change in FCR0

All Bits Low

Note 1 Boldface

bits are permanently low

Note 2

Bits 7–4 are driven by the input signals

Bit 7

This bit is the Divisor Latch Access Bit (DLAB) It

must be set high (logic 1) to access the Divisor

Latches of the Baud rate Generator during a Read

or Write operation or to have the Baud Out

(BOUT) signal appear on the BOUT pin It must be

set low (logic 0) to access any other register

63 PROGRAMMABLE BAUD RATE GENERATOR

The PC87306 contains two independently programmable

Baud rate Generators The 24 MHz oscillator frequency in-

put is divided by 13 resulting in a frequency of 18462 MHz

This is sent to each Baud rate Generator and divided by the

divisor of the associated UART The output frequency of the

Baud rate Generator (BOUT12) is 16c the baud rate

divisor

(frequency input) (baud rate c 16)

The output of each Baud rate Generator drives the transmit-

ter and receiver sections of the associated serial channel

Two 8-bit latches per channel store the divisor in a 16-bit

binary format These Divisor Latches must be loaded during

initialization to ensure proper operation of the Baud rate

Generator Upon loading either of the Divisor Latches a

16-bit Baud Counter is loaded Table 6-4 provides decimal

divisors to use with crystal frequencies of 24 MHz The os-

cillator input to the chip should always be 24 MHz to ensure

that the Floppy Disk Controller timing is accurate and that

the UART divisors are compatible with existing software

Using a divisor of zero is not recommended

TABLE 6-4 PC87306 UART Divisors

Baud Rates and Clock Frequencies

24 MHz Input Divided to 18462 MHz

Baud Rate

Decimal Divisor

Percent

for 16x Clock

Error (Note)

2304

1536

110

1047

1345

857

150

768

300

384

600

192

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

57600

115200

Note

The percent error for all baud rates except where indicated otherwise

is 02%

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