AD6634BCSLASHPCB datasheet(25/52 Pages) AD

25 / 52 page

REV. 0

AD6634

–25–

where, IN is the value of IN[13:0], EXP is the value of EXP[2:0],

and rCIC2 is the value of the 0x92 (rCIC2_QUIET[4:0], and

rCIC2_LOUD[4:0]) scale register.

rCIC2 Rejection

Table III illustrates the amount of bandwidth in percent of the

data rate into the rCIC2 stage. The data in this table may be

scaled to any other allowable sample rate up to 80 MHz in

Single Channel Mode or 40 MHz in Diversity Channel Mode.

Table III can be used as a tool to decide how to distribute the

decimation between rCIC2, CIC5, and the RCF.

Example Calculations

Goal: Implement a filter with an Input Sample Rate of 10 MHz

requiring 100 dB of Alias Rejection for a

±7 kHz pass band.

Solution: First determine the percentage of the sample rate that

is represented by the pass band.

kHz

MHz

FRACTION

=×

100

007

Find the –100 dB column on the right of Table III and look down

this column for a value greater than or equal to the pass-band

percentage of the clock rate. Then look across to the extreme

left column and find the corresponding rate change factor

(MrCIC2/LrCIC2). Referring to the table, notice that for a

MrCIC2/LrCIC2 of 4, the frequency having –100 dB of alias

rejection is 0.071 percent, which is slightly greater than the 0.07

percent calculated. Therefore, for this example, the maximum

bound on rCIC2 rate change is 4. A higher chosen MrCIC2/LrCIC2

means less alias rejection than the 100 dB required.

An MrCIC2/LrCIC2 of less than 4 would still yield the required

rejection; however, the power consumption can be minimized by

decimating as much as possible in this rCIC2 stage. Decimation in

rCIC2 lowers the data rate, and thus reduces power consumed in

subsequent stages. It should also be noted that there is more than

one way to get the decimation by 4. A decimation of 4 is the

same as an L/M ratio of 0.25. Thus any integer combination of

L/M that yields 0.25 will work (1/4, 2/8, or 4/16). However, for

the best dynamic range, the simplest ratio should be used. For

example, 1/4 gives better performance than 4/16.

Decimation and Interpolation Registers

rCIC2 decimation values are stored in register 0x90. This is a

12-bit register and contains the decimation portion less 1. The

interpolation portion is stored in register 0x91. This 9-bit value

holds the interpolation less one.

rCIC2 Scale

the circuit. The primary function is to store the scale value

computed in the sections above.

Bits 4–0 (rCIC2_LOUD[4:0]) of this register are used to contain

the scaling factor for the rCIC2 during conditions of strong

signals. These five bits represent the rCIC2 scalar calculated

above plus any external signal scaling with an attenuator.

Bits 9–5 (rCIC2_QUIET[4:0]) of this register are used to contain

the scaling factor for the rCIC2 during conditions of weak signals.

In this register, an external attenuator would not be used and is not

included. Only the value computed above is stored in these bits.

Bit 10 of this register is used to indicate the value of the external

exponent. If this bit is set LOW, then each external exponent

represents 6 dB per step as in the AD6600. If this bit is set to

HIGH, each exponent represents a 12 dB step.

Bit 11 of this register is used to invert the external exponent before

internal calculation. This bit should be set HIGH for gain ranging

ADCs that use an increasing exponent to represent an increasing signal

level. This bit should be set LOW for gain ranging ADCs that use

a decreasing exponent for representing an increasing signal level.

In applications that do not require the features of the rCIC2, it

may be by setting the L/M ratio to 1/1. This effectively bypasses

all circuitry of the rCIC2 except the scaling that is still effectual.

FIFTH ORDER CIC FILTER

The third signal processing stage, CIC5, implements a sharper

fixed-coefficient, decimating filter than rCIC2. The input rate

to this filter is fSAMP2. The maximum input rate is given by the

equation below. NCH equals 2 for diversity channel real input

mode; otherwise NCH equals 1. In order to satisfy this equation,

MrCIC2 can be increased, NCH can be reduced, or fCLK can be

increased (reference fractional rate input timing described in the

Input Timing section).

Table III. SSB rCIC2 Alias Rejection Table (fSAMP = 1) Bandwidth Shown in Percentage of fSAMP

MrCIC2/LrCIC2

–50 dB

–60 dB

–70 dB

–80 dB

–90 dB

–100 dB

1.79

1.007

0.566

0.318

0.179

0.101

1.508

0.858

0.486

0.274

0.155

0.087

1.217

0.696

0.395

0.223

0.126

0.071

1.006

0.577

0.328

0.186

0.105

0.059

0.853

0.49

0.279

0.158

0.089

0.05

0.739

0.425

0.242

0.137

0.077

0.044

0.651

0.374

0.213

0.121

0.068

0.038

0.581

0.334

0.19

0.108

0.061

0.034

0.525

0.302

0.172

0.097

0.055

0.031

0.478

0.275

0.157

0.089

0.05

0.028

0.439

0.253

0.144

0.082

0.046

0.026

0.406

0.234

0.133

0.075

0.043

0.024

0.378

0.217

0.124

0.07

0.04

0.022

0.353

0.203

0.116

0.066

0.037

0.021

0.331

0.19

0.109

0.061

0.035

0.02

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