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AD6634BC/PCB датащи(PDF) 18 Page - Analog Devices |
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AD6634BC/PCB датащи(HTML) 18 Page - Analog Devices |
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18 / 52 page ![]() REV. 0 –18– AD6634 PIN FUNCTION DESCRIPTIONS Mnemonic Type Function POWER SUPPLY VDD P 2.5 V Supply VDDIO P 3.3 V IO Supply GND G Ground INPUTS INA[13:0] 1 IA Input Data (Mantissa) EXPA[2:0] 1 IA Input Data (Exponent) IENA 2 I Input Enable—Input A INB[13:0] 1 IB Input Data (Mantissa) EXPB[2:0] 1 IB Input Data (Exponent) IENB 2 I Input Enable—Input B RESET I Active Low Reset Pin CLK I Input Clock PCLK I/O Link/Parallel Port Clock LACLKIN I Link Port A Data Ready LBCLKIN I Link Port B Data Ready SYNCA 1 I All Sync pins go to all four output channels. SYNCB 1 I All Sync pins go to all four output channels. SYNCC 1 I All Sync pins go to all four output channels. SYNCD 1 I All Sync pins go to all four output channels. CS1 I Chip Select CHIP_ID[3:0] 1 I Chip ID Selector CONTROL PAACK I Parallel Port A Acknowledge PAREQ O Parallel Port A Request PBACK I Parallel Port B Acknowledge PBREQ O Parallel Port B Request MICROPORT CONTROL D[7:0] I/O/T Bidirectional Microport Data A[2:0] I Microport Address Bus DS(RD)I Active Low Data Strobe (Active Low Read) DTACK(RDY)2 O/T Active Low Data Acknowledge (Microport Status Bit) R/W( WR)I Read Write (Active Low Write) MODE I Intel or Motorola Mode Select SERIAL PORT CONTROL SDI 1 I Serial Port Control Data Input SCLK 1 I Serial Port Control Clock OUTPUTS LIA–A O Level Indicator—Input A, Interleaved–Data A LIA–B O Level Indicator—Input A, Interleaved–Data B LIB–B O Level Indicator—Input B, Interleaved–Data B LIB–A O Level Indicator—Input B, Interleaved–Data A LACLKOUT O Link Port A Clock Output LBCLKOUT O Link Port B Clock Output LA[7:0] O Link Port A Output Data LB[7:0] O Link Port B Output Data PA[15:0] O Parallel Output Data Port A PB[15:0] O Parallel Output Data Port B PACH[1:0] O Parallel Output Port A Channel Indicator PBCH[1:0] O Parallel Output Port B Channel Indicator PAIQ O Parallel Port A I/Q Data Indicator PBIQ O Parallel Port B I/Q Data Indicator JTAG AND BIST TRST2 I Test Reset Pin TCLK 1 I Test Clock Input TMS 2 I Test Mode Select Input TDO O/T Test Data Output TDI 2 I Test Data Input NOTES 1Pins with a pull-down resistor of nominal 70 k Ω. 2Pins with a pull-up resistor of nominal 70 k Ω. |
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