AD6634BCSLASHPCB datasheet(42/52 Pages) AD

42 / 52 page

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AD6634

be dual-channel and determined by the state of the IENA pin. If the

IENA pin is low, the input detection is directed to LIA-A. If the

IENA pin is high, the input is directed to LIA-B. In either case,

Bit 4 determines the actual polarity of these signals.

Bits 2–0 determine the internal latency of the gain detect function.

When the LIA-A,B pins are made active, they are typically used

to change an attenuator or gain stage. Since this is prior to the

ADC, there is a latency associated with the ADC and with the

settling of the gain change. This register allows the internal delay

of the LIA-A,B signal to be programmed.

0x04 Lower Threshold B

This word is 10 bits wide and maps to the 10 most significant

bits of the mantissa. If the upper 10 bits of input port B are less

than or equal to this value, the lower threshold has been met. In

normal chip operation, this starts the dwell time counter. If the

input signal increases above this value, the counter is reloaded

and awaits the input to drop back to this level.

0x05 Upper Threshold B

This word is 10 bits wide and maps to the 10 most significant

bits of the mantissa. If the upper 10 bits of input port B are greater

than or equal to this value, the upper threshold has been met.

In normal chip operation, this will cause the appropriate LI pin

(LIB-A or LIB-B) to become active.

0x06 Dwell Time B

This sets the time that the input signal must be at or below the

lower threshold before the LI pin is deactivated. For the input

level detector to work, the dwell time must be set to at least 1.

If set to 0, the LI functions are disabled.

This is a 20-bit register. When the lower threshold is met following

an excursion into the upper threshold, the dwell time counter is

loaded and begins to count high speed clock cycles as long as the

input is at or below the lower threshold. If the signal increases above

the lower threshold, the counter is reloaded and waits for the signal

to fall below the lower threshold again.

0x07 Gain Range B Control Register

Bit 4 determines the polarity of LIB-A and LIB-B. If this bit is

clear then the LI signal is high when the upper threshold has

been exceeded. However, if this bit is set, the LI pin is low when

active. This allows maximum flexibility when using this function.

Bit 3 determines if the input consists of a single channel or TDM

channels such as when using the AD6600. If this bit is cleared,

a single ADC is assumed. In this mode, LIB-A functions as the

active output indicator. LIB-B provides the complement of LIB-A.

However if this bit is set, the input is determined to be dual

channel and determined by the state of the IENB pin. If the

IENB pin is low, the input detection is directed to LIB-A. If the

IENB pin is high, the input is directed to LIB-B. In either case,

Bit 4 determines the actual polarity of these signals.

Bits 2–0 determine the internal latency of the gain detect function.

When the LIB-A,B pins are made active, they are typically used

to change an attenuator or gain stage. Since this is prior to the

ADC, there is a latency associated with the ADC and with the

settling of the gain change. This register allows the internal delay

of the LIB-A,B signal to be programmed.

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