AD6634BCSLASHPCB datasheet(36/52 Pages) AD

36 / 52 page

REV. 0

–36–

AD6634

LINK PORT

A OR B

AGC A I, Q

(4 BYTES)

AGC B I, Q

(4 BYTES)

AGC A I, Q

(4 BYTES)

AGC B I, Q

(4 BYTES)

ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 0

LINK PORT

A OR B

AGC A I, Q

(4 BYTES)

AGC A RSSI

(4 BYTES)

AGC B I, Q

(4 BYTES)

AGC B RSSI

(4 BYTES)

ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 1

LINK PORT A

AGC A I, Q

(4 BYTES)

AGC A RSSI

(4 BYTES)

AGC A I, Q

(4 BYTES)

AGC A RSSI

(4 BYTES)

AGC B I, Q

(4 BYTES)

AGC B RSSI

(4 BYTES)

AGC B I, Q

(4 BYTES)

AGC B RSSI

(4 BYTES)

LINK PORT B

ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 1, BIT 2 = 0

Figure 42. Link Port Data from AGC

Note that Bit 0 = 1 Bit 1 = 0, and Bit 2 = 1 is not a valid

configuration. Bit 2 must be set to 0 to output AGC A IQ and

RSSI words on link port A, and AGC B IQ and RSSI words

on link port B.

Link Port Timing

Both link ports run off of PCLK, which can be externally provided

to the chip (Addr 0x1E Bit 0 = 0) or generated from the master

clock of the AD6634 (Addr 0x1E Bit 0 = 1). This register boots

to 0 (Slave mode) and allows the user to control the data rate

coming from the AD6634. PCLK can be run as fast as 100 MHz.

The link port provides a 1-byte data-word (LA[7:0], LB[7:0]

pins) and output clocks (LACLKOUT, LBCLKOUT pins) in

response to a ready signals (LACLKIN, LBCLKIN pins) from

the receiver. Each link port transmits eight bits on each edge of

LCLKOUT, requiring eight LCLKOUT cycles to complete

transmission of the full 16 bytes of a TigerSHARC quad-word.

D0 D1 D2 D3

D15

D0 D1 D2

NEXT QUAD-WORD

TigerSHARC READY TO

RECEIVE QUAD-WORD

WAIT >= 6 CYCLES

TigerSHARC READY TO

RECEIVE NEXT QUAD-WORD

LCLKIN

LCLKOUT

LDAT[7:0]

Figure 43. Link Port Data Transfer

Due to the TigerSHARC link port protocol, the AD6634 must

wait at least six PCLK cycles after the TigerSHARC is ready to

receive data, as indicated by the TigerSHARC setting the respective

AD6634 LCLKIN pin high. Once the AD6634 link port has

waited the appropriate number of PCLK cycles and has begun

transmitting data, the TigerSHARC does a connectivity check

by sending the AD6634 LCLKIN low and then high while the

data is being transmitted. This tells the AD6634 link port that the

TigerSHARC’s DMA is ready to receive the next quad-word after

completion of the current quad-word. Because the connectivity

check is done in parallel to the data transmission, the AD6634

is able to stream uninterrupted data to the TigerSHARC.

The length of the wait before data transmission is a 4-bit

programmable value in the link port control registers (0x1B and

0x1D Bits 6–3). This value allows the AD6634 PCLK and

the TigerSHARC PCLK to be run at different rates and

out of phase.

WAIT

ceil

LCLK

LCLK TSHARC

≥×













WAIT ensures that the amount of time the AD6634 needs to wait

to begin data transmission is at least equal to the minimum amount

of time the TigerSHARC is expecting it to wait. If the PCLK of

the AD6634 is out of phase with the PCLK of the TigerSHARC

and the argument to the ceil() function is an integer, WAIT must

be strictly greater than the value given in the above formula.

If the LCLKs are in phase, the maximum output data rate is:

LCLK

LCLK TSHARC

≤×

otherwise it is:

LCLK

LCLK TSHARC

≤×

TigerSHARC Configuration

Since the AD6634 is always the transmitter in this link and the

TigerSHARC is always the receiver, the values in Table IX can

be programmed into the LCTL register for the link port used to

receive AD6634 output data. User means that the actual register

value depends on the user’s application.

Table IX. TigerSHARC LCTLx Register Configuration

VERE

SPD

User

LTEN

PSIZE

TTOE

CERE

LREN

RTOE

MEMORY MAPS

0x00–0x7F: Coefficient Memory(CMEM)

This is the Coefficient Memory(C-MEM) used by the RCF

(See Table X). It is memory mapped as 128 words by 20 bits.

A second 128 words of RAM may be accessed via this same

location by writing Bit 8 of the RCF control register high at

channel address 0xA4. The filter calculated will always use the

same coefficients for I and Q. By using memory from both of these

128 blocks, a filter up to 160 taps can be calculated. Multiple

filters can be loaded and selected with a single internal access

to the Coefficient Offset register at channel address 0xA3.

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