AD6634BCSLASHPCB datasheet(38/52 Pages) AD

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AD6634

Hold-Off Counter hits a value of 1. If the Frequency Hold-Off

Counter is set to 1, the register will be updated as soon as the

shadow is written.

0x86: NCO Frequency Register 1

This register represents the 16 MSBs of the NCO Frequency

word. These bits are shadowed and are not updated to the regis-

ter used for the processing until the channel is either brought

out of SLEEP or a Soft_SYNC or Pin_SYNC has been issued.

In the latter two cases the register is updated only when the

Frequency Hold-Off Counter hits a value of 1. If the Frequency

Hold-Off Counter is set to 1, the register will be updated as

soon as the shadow is written.

0x87: NCO Phase Offset Register

This register represents a 16-bit phase offset to the NCO. It can

be interpreted as values ranging from 0 to just under 2 .

0x88: NCO Control Register

This 9-bit register controls features of the NCO and the channel.

The bits are defined below. For more details, the NCO section

should be consulted.

Bits 8–7 of this register choose which of the four SYNC pins are

used by the channel. The SYNC pin selected can be used to

initiate a START, HOP, or timing adjustment to the channel.

The Synchronization section provides more details on this.

Bit 6 of this register defines whether the A or B input port is

used by the channel. If this bit is low, the A Input Port is

selected; and if this bit is high, the B Input Port is selected.

Each input port consists of a 14-bit input mantissa(INx[13:0]),

a 3-bit exponent(EXPx[2:0]), and an input enable pin IENx.

The x represents either A or B.

Bits 5–4 determine how the sample clock for the channel is

derived from the high speed CLK signal. There are four pos-

sible choices. Each is defined below but for further details, the

NCO section of the data sheet should be consulted.

When these bits are 00, the input sample rate (fSAMP) of the

channel is equal to the rate of the high speed CLK signal. When

IEN is low, the data going into the channel is masked to 0. This

is an appropriate mode for TDD systems where the receiver

may wish to mask off the transmitted data yet still remain in the

proper phase for the next receive burst.

When these bits are 01, the input sample rate is determined by

the fraction of the rising edges of CLK on which the IEN input

is high. For example, if IEN toggles on every rising edge of

CLK, the IEN signal will only be sampled high on one out of

every two rising edges of CLK, which means that the input

sample rate fSAMP will be one-half the CLK rate.

When these bits are 10, the input sample rate is determined by

the rate at which the IEN pin toggles. The data that is captured

on the rising edge of CLK after IEN transitions from low to

high is processed. When these bits are 11, the accumulator and

sample CLK are determined by the rate at which the IEN pin

toggles. The data that is captured on the rising edge of CLK

after IEN transitions from high to low is processed. For example,

control modes 10 and 11 can be used to allow interleaved data

from either the A or B input ports and then assigned to the

respective channel. The IEN pin selects the data such that a

channel could be configured in mode 10 and another could be

configured in mode 11.

Bit 3 determines whether or not the phase accumulator of the

NCO is cleared when a Hop occurs. The Hop can originate

from either the Pin_SYNC or Soft_SYNC. When this bit is set

to 0, the Hop is phase continuous and the accumulator is not

cleared. When this bit is set to 1, the accumulator is cleared to 0

before it begins accumulating the new frequency word. This is

appropriate when multiple channels are hopping from different

frequencies to a common frequency.

Bits 2–1 control whether or not the dithers of the NCO are

activated. The use of these features is heavily determined by the

system constraints. Consult the NCO section of the data sheet

for more detailed information on the use of dither.

Bit 0 of this register allows the NCO Frequency translation stage

to be bypassed. When this occurs the data from the A Input Port is

passed down the I path of the channel and the data from the B

Input Port is passed down the Q path of the channel. This

allows a real filter to be performed on baseband I and Q data.

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