AD6634BCSLASHPCB datasheet(24/52 Pages) AD

24 / 52 page

REV. 0

–24–

AD6634

Mode 10: Clock on IEN Transition to High

In this mode, data is clocked into the chip only on the first clock

edge after the rising transition of the IEN line. Although data is

latched only on the first valid clock edge, the back end process-

ing (rCIC2, CIC5, and RCF) continues on each available clock

that may be present, similar to Mode 01. The NCO phase accu-

mulator is incremented only once for each new input data sample

and not once for each input clock.

Mode 11: Clock on IEN Transition to Low

In this mode, data is clocked into the chip only on the first clock

edge after the falling transition of the IEN line. Although data is

latched only on the first valid clock edge, the back end process-

ing (rCIC2, CIC5, and RCF) continues one each available

clock that may be present, similar to Mode 01. The NCO phase

accumulator is incremented only once for each new input data

sample and not once for each input clock.

WB Input Select

Bit 6 in this register controls which input port is selected for signal

processing. If this bit is set high, input port B (INB, EXPB, and

IENB) is connected to the selected filter channel. If this bit is

cleared, input port A (INA, EXPA, and IENA) is connected to

the selected filter channel.

Sync Select

Bits 7 and 8 of this register determine which external sync pin is

associated with the selected channel. The AD6634 has four sync

pins named SYNCA, SYNCB, SYNCC, and SYNCD. Any of

these sync pins can be associated with any of the four receiver

channels within the AD6634. Additionally, if only one sync

signal is required for the system, all four receiver channels can

reference the same sync pulse. Bit value 00 is channel A, 01 is

channel B, 10 is channel C, and 11 is channel D.

SECOND ORDER rCIC FILTER

The rCIC2 filter is a second order cascaded resampling integra-

tor comb filter. The resampler is implemented using a unique

technique that does not require the use of a high speed clock,

thus simplifying the design and saving power. The resampler

allows for noninteger relationships between the master clock

and the output data rate, which allows easier implementation of

systems that are either multimode or require a master clock that

is not a multiple of the data rate to be used.

Interpolation up to 512 and decimation up to 4096 is allowed in

the rCIC2. The resampling factor for the rCIC2 (L) is a 9-bit

integer. When combined with the decimation factor M, a 12-bit

number, the total rate change can be any fraction in the form of:

rCIC

≤

The only constraint is that the ratio L/M must be less than or equal

to one. This implies that the rCIC2 decimates by 1 or more.

Resampling is implemented by apparently increasing the input

sample rate by the factor L, using zero stuffing for the new data

samples. Following the resampler is a second order cascaded

integrator comb filter. Filter characteristics are determined only

by the fractional rate change (L/M).

The filter can process signals at the full rate of the input port,

80 MHz. The output rate of this stage is given by the equation:

SAMP

rCIC

SAMP

rCIC

Both LrCIC2 and MrCIC2 are unsigned integers. The interpolation

rate (LrCIC2) may be from 1 to 512 and the decimation (MrCIC2)

may be between 1 and 4096. The stage can be bypassed by

setting the decimation to 1/1. The frequency response of the

rCIC2 filter is given by the following equations.

rCIC

SAMP

rCIC

() =

















() =





























–

sin

The gain and pass-band droop of the rCIC2 should be calculated

by the equations above, as well as the filter transfer equations that

follow. Excessive pass-band droop can be compensated for in the

RCF stage by peaking the pass band by the inverse of the roll-off.

The scale factor, SrCIC2 is a programmable unsigned 5-bit between

0 and 31. This serves as an attenuator that can reduce the gain

of the rCIC2 in 6 dB increments. For the best dynamic range,

SrCIC2 should be set to the smallest value possible (i.e., lowest

attenuation) without creating an overflow condition. This can

be safely accomplished using the equation below, where

input_level is the largest fraction of full scale possible at the input

to the AD6634 (normally 1). The rCIC2 scale factor is always

used whether or not the rCIC2 is bypassed.

Moreover, there are two scale registers (rCIC2_LOUD[4:0]

Bits 4–0 in x92) and (rCIC2_QUIET[4:0] Bits 9–5 in x92) that are

used in conjunction with the computed SrCIC2, which determines

the overall rCIC2 scaling. The SrCIC2 value must be summed

with the values in each respective scale registers and ExpOff to

determine the scale value that must be placed in the rCIC2 scale

and decimation rates must be adjusted to validate this equation.

The ceil function denotes the next whole integer and the floor func-

tion denotes the previous whole integer. For example, the ceil(4.5)

is 5 while the floor(4.5) is 4.

scaled_input

ExpInv

scaled_input

ExpInv

MOD Exp

rCIC

–MOD 7 – Exp + rCIC2,

=×

()

232

–,

ceil

floor

input level

rCIC









××









































= ()

log

–

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