AD6634BCSLASHPCB datasheet(41/52 Pages) AD

41 / 52 page

REV. 0

AD6634

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the Q output data through the microport. To accomplish this,

the Map RCF data to BIST bit in the RCF Control register 2,

0xA9, should be set high. Sixteen bits of Q data can then be read

through the microport in either the 8 + 4, 12 + 4, 12-bit linear,

or 16-bit linear output modes. This data may come from either

the formatted RCF output or the CIC5 output.

0xA7: BIST Control Register

This register controls the number of outputs of the RCF or CIC

filter that are observed when a BIST test is performed. The BIST

signature registers at addresses 0xA5 and 0xA6 will observe this

number of outputs and then terminate. The loading of this

utilize the BIST circuitry are defined in the BIST section.

0xA8: RAM BIST Control Register

This register is used to test the memories of the AD6634 should

they ever be suspected of a failure. Bit 0 of this register is written

with a 1 when the channel is in SLEEP and the user waits for

1600 CLKs and then polls the bits. If Bit 1 is high, the CMEM

failed the test; and if Bit 2 is high, the data memory used by the

RCF failed the test.

0xA9: Output Control Register

Bit 9 of this register allows the RCF or CIC5 data to be mapped

to the BIST registers at addresses 0xA5 and 0xA6. When this bit

is 0, the BIST register is in signature mode and ready for a self-test

to be run. When this bit is 1, the output data from the RCF after

formatting or the CIC5 data is mapped to these registers and

can be read through the microport.

Bits 5 determines the word length used by the parallel port. If this

bit is 0, the parallel port uses 12-bit words for I and Q. If this

bit is 1, the parallel port uses 16-bit words for I and Q. When the

fixed-point output option is chosen from the RCF control

formatter of the RCF.

Remaining bits in this register are reserved and should be written

low when programming.

In order to access the Input/Output Port Registers, Bit 5 of

SLEEP

is then written with the address to the correct Input Port Register.

Input Port Control Registers

The Input Port control register enables various input related

features used primarily for input detection and level control.

Depending on the mode of operation, up to four different signal

paths can be monitored with these registers. These features are

accessed by setting Bit 5 of external address 3 (Sleep Register)

and then using the CAR (external address 6) to address the

eight locations available.

Response to these settings is directed to the LIA-A, LIA-B,

LIB-A, and LIB-B Pins.

0x00 Lower Threshold A

This word is 10 bits wide and maps to the 10 most significant

bits of the mantissa. If the upper 10 bits of input port A are less

than or equal to this value, the lower threshold has been met. In

normal chip operation, this starts the dwell time counter. If the

input signal increases above this value, the counter is reloaded

and awaits the input to drop back to this level.

0x01 Upper Threshold A

This word is 10 bits wide and maps to the 10 most significant

bits of the mantissa. If the upper 10 bits of input port A are

greater than or equal to this value, the upper threshold has been

met. In normal chip operation, this will cause the appropriate LI

pin (LIA-A or LIA-B) to become active.

0x02 Dwell Time A

This sets the time that the input signal must be at or below the

lower threshold before the LI pin is deactivated. For the input

level detector to work, the dwell time must be set to at least 1.

If set to 0, the LI functions are disabled.

This is a 20-bit register. When the lower threshold is met following

an excursion into the upper threshold, the dwell time counter is

loaded and begins to count high speed clock cycles as long as

the input is at or below the lower threshold. If the signal increases

above the lower threshold, the counter is reloaded and waits for

the signal to fall below the lower threshold again.

0x03 Gain Range A Control Register

Bit 4 determines the polarity of LIA-A and LIA-B. If this bit is

clear, the LI signal is high when the upper threshold has been

exceeded. However, if this bit is set, the LI pin is low when active.

This allows maximum flexibility when using this function.

Bit 3 determines if the input consists of a single channel or

TDM channels such as when using the AD6600. If this bit is

cleared, a single ADC is assumed. In this mode, LIA-A functions

as the active output indicator. LIA-B provides the complement

of LIA-A. However, if this bit is set, the input is determined to

Table XIV. Memory Map for Input Port Control Registers

Channel

Bit

Address

Width

Comments

Lower Threshold A

9–0:

Lower Threshold for Input A

Upper Threshold A

9–0:

Upper Threshold for Input A

Dwell Time A

19–0: Minimum Time Below Lower Threshold A

Gain Range A Control Register

Output Polarity LIA-A and LIA-B

Interleaved Channels

2–0:

Linearization Hold-Off Register

Lower Threshold B

9–0:

Lower Threshold for Input B

Upper Threshold B

9–0:

Upper Threshold for Input B

Dwell Time B

19–0: Minimum Time Below Lower Threshold B

Gain Range B Control Register

Output Polarity LIB-A and LIB-B

Interleaved Channels

2–0:

Linearization Hold-Off Register

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