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AD6634BC/PCB датащи(PDF) 44 Page - Analog Devices

номер детали AD6634BC/PCB
подробное описание детали  80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP)
PDF  52 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD6634BC/PCB датащи(HTML) 44 Page - Analog Devices

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AD6634
Table XV. Memory Map for Output Port Control Registers (continued)
Channel
Bit
Address
Register
Width
Comments
16
AGC B Loop Gain
8
7–0:
K Parameter
17
AGC B Pole Location
8
7–0:
P Parameter
18
AGC B Average Samples
6
5–2:
Scale for CIC Decimator
1–0:
Number of Averaging Samples
19
AGC B Update Decimation
12
11–0: CIC Decimation
1A
Parallel A Control
8
7–6:
Reserved
5:
Parallel Port Data Format
1:
8-Bit Parallel I, Q
0:
16-Bit Interleaved I, Q
4:
Channel 3
3:
Channel 2
2:
Channel 1/AGC B Enable
1:
Channel 0/AGC A Enable
0:
AGC_CH Select
1:
Data Comes from AGCs
0:
Data Comes from Channels
1B
Link A Control
8
7:
Link Port A Enable
6–3:
Wait
2:
No RSSI Word
1:
Don’t Output RSSI Word
0:
Output RSSI Word
1:
Channel Data Interleaved
1:
2-Channel Mode/Separate AB
0:
4-Channel Mode/AB Same Port
0:
AGC_CH Select
1:
Data Comes from AGCs
0:
Data Comes from Channels
1C
Parallel B Control
8
7–6: Reserved
5:
Parallel Port Data Format
1:
8-Bit Parallel I, Q
0:
16-Bit Interleaved I, Q
4:
Channel 3
3:
Channel 2
2:
Channel 1/AGC B Enable
1:
Channel 0/AGC A Enable
0:
AGC_CH Select
1:
Data Comes from AGCs
0:
Data Comes from Channels
1D
Link B Control
8
7:
Link Port B Enable
6–3:
Wait
2:
No RSSI Word
1:
Don’t Output RSSI Word
0:
Output RSSI Word
1:
Channel Data Interleaved
1:
2-Channel Mode/Separate AB
0:
4-Channel Mode/AB Same Port
0:
AGC_CH Select
1:
Data Comes from AGCs
0:
Data Comes from Channels
1E
Port Clock Control
3
2–1:
PCLK Divisor
0:
PCLK Master/Slave
*
0:
Slave
1:
Master
*PCLK boots as slave.



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