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AD6634

GENERAL DESCRIPTION

The AD6634 is a multimode 4-channel digital receive signal pro-

cessor (RSP) capable of processing up to two WCDMA channels.

Each channel consists of four cascaded signal processing elements:

a frequency translator, two fixed coefficient decimating filters,

and a programmable coefficient decimating filter. Each input port

has input level threshold detection circuitry and an AGC con-

troller for accommodating large dynamic ranges or situations

where gain ranging converters are used. Dual 16-bit parallel output

ports accommodate high data rate WBCDMA applications. On-chip

interpolating half-band can also be used to further increase the

output rate. In addition, each parallel output port has a digital

AGC for output data scaling. Link port outputs are provided to

enable glueless interfaces to ADI’s TigerSHARC® DSP core.

The AD6634 is part of Analog Devices’ SoftCell

® Multicarrier

transceiver chipset designed for compatibility with Analog Devices’

family of high sample rate IF sampling ADCs (AD9238/AD6645

12- and 14-bit). The SoftCell receiver comprises a digital receiver

capable of digitizing an entire spectrum of carriers and digitally

selecting the carrier of interest for tuning and channel selection.

This architecture eliminates redundant radios in wireless base

station applications.

High dynamic range decimation filters offer a wide range of

decimation rates. The RAM-based architecture allows easy

reconfiguration for multimode applications.

The decimating filters remove unwanted signals and noise from

the channel of interest. When the channel of interest occupies less

bandwidth than the input signal, this rejection of out-of-band

noise is called processing gain. By using large decimation factors,

this processing gain can improve the SNR of the ADC by 30 dB

or more. In addition, the programmable RAM coefficient filter

allows antialiasing, matched filtering, and static equalization func-

tions to be combined in a single, cost-effective filter. Half-band

interpolating filters at the output are used in WCDMA applications

to increase the output rate from 2

× to 4× of the chip rate. The

AD6634 is also equipped with two independent automatic gain

control (AGC) loops for direct interface to a RAKE receiver.

The AD6634 is compatible with standard ADC converters such

as the AD664x, AD923x, AD943x, and the AD922x families of

data converters. The AD6634 is also compatible with the AD6600

diversity ADC, providing a cost and size reduction path.

*TigerSHARC and SoftCell are registered trademarks of Analog Devices, Inc.

ARCHITECTURE

The AD6634 has four signal processing stages: a frequency

translator, second order resampling cascaded integrator comb

FIR filters (rCIC2), a fifth order cascaded integrator comb FIR

filter (CIC5), and a RAM coefficient FIR filter (RCF). Multiple

modes are supported for clocking data into and out of the chip

and provide flexibility for interfacing to a wide variety of digitizers.

Programming and control are accomplished via serial and/or

microprocessor interfaces.

Frequency translation is accomplished with a 32-bit, complex,

numerically controlled oscillator (NCO). Real data entering this

stage is separated into inphase (I) and quadrature (Q) components.

This stage translates the input signal from a digital intermediate

frequency (IF) to digital baseband. Phase and amplitude dither

may be enabled on-chip to improve spurious performance of the

NCO. A phase-offset word is available to create a known phase

relationship among multiple AD6634s or between channels.

Following frequency translation is a resampling, fixed coefficient,

high speed, second order, resampling cascade integrator comb

(rCIC2) filter that reduces the sample rate based on the ratio

between the decimation and interpolation registers.

The next stage is a fifth order cascaded integrator comb (CIC5)

filter whose response is defined by the decimation rate. The purpose

of this filter is to reduce the data rate to the final filter stage so

that it can calculate more taps per output.

The final stage is a sum-of-products FIR filter with program-

mable 20-bit coefficients, and decimation rates programmable

from 1 to 256 (1–32 in practice). The RAM coefficient FIR filter

(RCF in the Functional Block Diagram) can handle a maximum

of 160 taps.

The next stage is a fixed coefficient half-band interpolation filter

where data from different channels is combined together and

interpolated by a factor of 2. Next, an AGC section with a gain

range of 96.3 dB is available. This AGC section is completely

programmable in terms of its response. Two each of half-band

filters and AGCs are present in the AD6634, as shown in the

Functional Block Diagram. These half-band filters and AGC

sections can be bypassed independent of each other.

The overall filter response for the AD6634 is the composite of all

decimating and interpolating stages. Each successive filter stage is

capable of narrower transition bandwidths but requires a greater

number of CLK cycles to calculate the output. More decimation

in the first filter stage will minimize overall power consumption.

Data from the chip is interfaced to the DSP via either a high

speed parallel port or a TigerSHARC compatible link port.

Figure 1a illustrates the basic function of the AD6634: to select and

filter a single channel from a wide input spectrum. The frequency

translator tunes the desired carrier to baseband. Figure 1b shows

the combined filter response of the rCIC2, CIC5, and RCF.

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