AD6634BCSLASHPCB datasheet(45/52 Pages) AD

45 / 52 page

REV. 0

AD6634

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In order to access the Input/Output Port Registers, Bit 5 of

SLEEP register (on external memory map) should be written

high. The CAR is then written with the address to the correct

Output Port Register.

0x08 Port A Control Register

Bit 0 enables the use of interpolating half-band filter corresponding

to Port A. Half-band A can be used to interleave the data streams

of multiple channels and interpolate by two providing a maximum

output data rate of 4

the chip rate. It can be configured to

listen to all four channels; channels 0, 1, 2, 3; channels 0, 1, 2;

channels 0, 1; or only channel 0. Half-band A is bypassed when bit

0 = 1, in which case the outputs of the RCFs are directly sent to

the AGC. The channel data streams are still interleaved with the

half-band bypassed, but they are not filtered and interpolated. The

maximum data rate from this configuration would be 2

the

chip rate.

0x09 Port B Control Register

Bit 0 enables the use of interpolating half-band filter corresponding

to Port B. Half-band B can be used to interleave the data streams

of multiple channels and interpolate by 2 providing a maximum

output data rate of 4

the chip rate. It can be configured to

listen to channels 2 and 3; or only channel two. Half-band B is

bypassed when bit 0 = 1, in which case the outputs of the RCFs

are directly sent to the AGC. The channel data streams are still

interleaved with the half-band bypassed, but they are not filtered

and interpolated. The maximum data rate from this configura-

tion would be 2

the chip rate.

0x0A AGC A Control Register

This 8-bit register controls features of the AGC A. The bits are

defined below:

Bits 7–5 define the output word length of the AGC. The output

word can be 4–8, 10, 12, or 16 bits wide. The control register

bit representation to obtain different output word lengths is

given in the Memory Map Table.

Bit 4 of this register sets the mode of operation for the AGC.

When this bit is 0, the AGC tracks to maintain the output signal

level and when this bit is 1, the AGC tracks to maintain a con-

stant clipping error. Consult the AGC section for more details

about these modes.

Bits 3–1 are used to configure the synchronization of the AGC.

The CIC decimator filter in the AGC can be synchronized to an

external sync signal to output an update sample for the AGC error

calculation and filtering. This way the AGC gain changes can be

synchronized to an external block like a Rake receiver. Whenever

an external sync signal is received, the hold-off counter at 0x0B

is loaded and begins to count down. When the counter reaches

one, the CIC filter dumps an update sample and starts working

towards a new update sample. The AGC can be initialized on

each SYNC or only on the first SYNC.

Bit 3 is used to issue a command to the AGC to SYNC immedi-

ately. If this bit is set, the CIC filter will update the AGC with a

new sample immediately and start operating towards the next

update sample. The AGC can be synchronized by the microport

control interface using this method.

Bit 2 is used to determine whether the AGC should initialize on

a SYNC or not. When this bit is set, the CIC filter is cleared and

new values for CIC decimation, number of averaging samples,

CIC scale, Signal gain GS, gain K, and pole parameter P are

loaded. When Bit 2 = 0, the above-mentioned parameters are

not updated and the CIC filter is not cleared. In both cases, an

AGC update sample is output from the CIC filter and the

decimator starts operating towards the next output sample

whenever a SYNC occurs.

Bit 1 is used to ignore repetitive synchronization signals. In

some applications, the synchronization signal may occur peri-

odically. If this bit is clear, each synchronization request will

resynchronize the AGC. If this bit is set, only the first occur-

rence will cause the AGC to synchronize and will update AGC

gain values periodically depending on the decimation factor of

the AGC CIC filter.

Bit 0 is used to bypass the AGC section, when it is set. The

23-bit representation from interpolating half-band filters is still

reduced to a lower bit width representation as set by Bits 7–5 of

the AGC A Control Register. A truncation at the output of the

AGC accomplishes this task.

0x0B AGC A Hold-Off Counter

The AGC A Hold-Off counter is loaded with the value written

to this address when either a Soft_SYNC or Pin_SYNC comes

into the channel. The counter begins counting down so when it

reaches one, a SYNC is given to AGC A. This SYNC may or

may not initialize the AGC, as defined by the control word. The

AGC loop is updated with a new sample from the CIC filter

whenever a SYNC occurs. If this register is written to 1, the

AGC will be updated immediately when the SYNC occurs. If

this register is written to a 0, the AGC cannot be synchronized.

0x0C AGC A Desired Level

This 8-bit register contains the desired output power level or

desired clipping level depending on the mode of operation. This

desired Request R level can be set in dB from 0 to –23.99 in

steps of 0.094 dB. 8-bit binary floating-point representation is

used with 2-bit exponent followed by 6-bit mantissa. Mantissa is

in steps of 0.094 dB and exponent in 6.02 dB steps. For example,

10’100101 represents 2

6.02 + 37

0.094 = 15.518 dB.

0x0D AGC A Signal Gain

This register is used to set the initial value for a signal gain used in

the gain multiplier. This 12-bit value sets the initial signal gain

between 0 and 96.296 dB in steps of 0.024 dB. 12-bit binary

floating-point representation is used with 4-bit exponent fol-

lowed by 8-bit mantissa. For example, 0111’10001001 is

equivalent to 7

6.02 + 137

0.024 = 45.428 dB.

0x0E AGC A Loop Gain

This 8-bit register is used to define the open loop gain, K. Its

value can be set from 0 to 0.996 in steps of 0.0039. This value of K

is updated in the AGC loop each time the AGC is initialized.

0x0F AGC A Pole Location

This 8-bit register is used to define the open loop filter pole loca-

tion P. Its value can be set from 0 to 0.996 in steps of 0.0039.

This value of P is updated in the AGC loop each time the AGC is

initialized. This open loop pole location will directly impact the

closed loop pole locations as explained in the AGC section.

0x10 AGC A Average Samples

This 6-bit register contains the scale used for the CIC filter and

the number of power samples to be averaged before being fed to

the CIC filter.

Bits 5–2 define the scale used for the CIC filter.

Bits 1–0 define the number of samples to be averaged before

they are sent to the CIC decimating filter. This number can be

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