AD6634BCSLASHPCB datasheet(43/52 Pages) AD

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AD6634

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Table XV. Memory Map for Output Port Control Registers

Channel

Bit

Address

Width

Comments

Port A Control Register

Port A Enable

2–1:

HB A Signal Interleaving

All 4 Channels

Chs 0, 1, 2

Chs 0,1

Ch 0

Bypass

Port B Control Register

Port B Enable

HB A Signal Interleaving

1Chs 2, 3

0Ch 2

Bypass

AGC A Control Register

7–5:

Output Word Length

111

4 Bits

110

5 Bits

101

6 Bits

100

7 Bits

011

8 Bits

010

10 Bits

001

12 Bits

000

16 Bits

Clipping Error

Maintain Level of Clipping Error

Maintain Output Signal Level

Sync Now

Init on Sync

First Sync Only

Bypass

AGC A Hold-Off Counter

15–0: Hold Off Value

AGC A Desired Level

7–0:

Desired Output Power Level or Clipping Energy

(R Parameter)

AGC A Signal Gain

11–0: GS Parameter

AGC A Loop Gain

7–0:

K Parameter

AGC A Pole Location

7–0:

P Parameter

AGC A Average Samples

5–2:

Scale for CIC Decimator

1-0:

Number of Averaging Samples

AGC A Update Decimation

11–0: CIC Decimation Ratio

AGC B Control Register

7–5:

Output Word Length

112

4 Bits

110

5 Bits

102

6 Bits

101

7 Bits

011

8 Bits

010

10 Bits

001

12 Bits

000

16 Bits

Clipping Error

Maintain Level of Clipping Error

Maintain Output Signal Level

Sync Now

Init on Sync

First Sync Only

Bypass

AGC B Hold-Off Counter

15–0: Hold Off Value

AGC B Desired Level

7–0:

Desired Output Power Level or Clipping Energy

(R Parameter)

AGC B Signal Gain

11–0: GS Parameter

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